CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 129

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.7.5
The following explains the SRAM Write operation accomplished through a table(s) of up to eight devices with the following
parameters (TLSZ = 01 (binary)). The hardware diagram for this table is shown in Figure 6-71. The following assumes that SRAM
access is achieved through Ayama 10000 device number 0. Figure 6-72 and Figure 6-73 show the timing diagram for device
number 0 and device number 7, respectively.
Document #: 38-02069 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[25:23] for CYNSE10512, SADR[24:22] for CYNSE10256, SADR[23:21] for
CYNSE10128 on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write because burst WRITEs into the SRAM
are not supported.
DQ[71:0]
CMDV
CMD[10:0]
SSF, SSV
SRAM Write with a Table of up to Eight Devices
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
Figure 6-71. Hardware Diagram of a Block of Eight Devices
LHO[1]
3
3
3
LHO[1]
2
LHI
2
2
LHI
LHO[1]
LHI
1
CONFIDENTIAL
1
1
PRELIMINARY
LHO[1]
0
0
0
Ayama 10000 #6
Ayama 10000 #7
Ayama 10000 #4
Ayama 10000 #2
Ayama 10000 #3
Ayama 10000 #5
Ayama 10000 #0
Ayama 10000 #1
LHO[0]
6
6
6
6
6
6
6
6
LHO[0]
LHI
LHI
5
5
5
5
5
5
5
5
LHI
LHO[0]
4
4
4
4
4
4
4
4
LHO[0]
LHI
LHI
LHI
LHI
LHI
LHO[1] LHO[0]
3
3
3
3
3
LHO[0]
2
2
2
2
2
LHO[0]
1
1
1
1
1
LHO[0]
BHO[2]
BHO[0]
BHO[1]
0
0
0
0
0
BHO[0]
BHO[1]
BHO[2]
CYNSE10512
CYNSE10256
CYNSE10128
Page 129 of 153
SRAM
[+] Feedback
[+] Feedback