CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 53

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Burst Read operation sequence:
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of RBURREG are complete.
On the last data transfer, the Ayama 10000 drives the EOT signal HIGH.
Cycle (4 + 2n): The selected device drives the DQ[71:0] to a three-state condition, and drives ACK and EOT signals LOW.
At the termination of cycle (4 + 2n), the selected device floats ACK and EOT to a three-state condition. The burst Read operation
is complete and the next operation can begin.
6.3.3
Data output of the Read Parity command should be ignored. Read Parity is a blocking operation only on the cycles as the normal
Read operation even though the parity status signal (PARERR) is valid TLSZ cycles later. Figure shows an example of the
PARERR update timing diagram with TLSZ set to “10” (two additional cycles of latency) to a total of eight cycles (six Read cycles
plus two TLSZ cycles).
6.4
The Write command can be issued to write to the data array, mask array, NSE-associated SRAMs or internal registers. The Write
can be a single or burst Write (Table 6-3). Burst Write can only be issued for accesses to the data or mask array locations. SRAM
Write operation is covered in Section 6.7.4 to Section 6.7.6. The Write command is also used to issue the Parallel Write command.
Note that when Parity feature is enabled masks will be ignored and all bits will be written as presented in the DQ bus.
Document #: 38-02069 Rev. *F
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the address location on the DQ[71:0] bus and drives the ACK signal
on the DQ bus. The host ASIC selects the Ayama 10000 device where ID[4:0] matches the DQ[25:21] lines. If
DQ[25:21] = 11111, the host ASIC selects the Ayama 10000 device with the LDEV bit set.
HIGH.
Read Parity
Write Command
CMD[10:2]
CMD[1:0]
CMDV
CLK2X
PHS_L
ACK
EOT
DQ
Figure 6-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
Address
cycle
Read
A B
1
cycle
2
cycle
3
CONFIDENTIAL
PRELIMINARY
cycle
4
0
cycle
Data0
5
cycle
6
0
cycle
Data1
7
cycle
8
0
cycle
Data2
9
cycle
10
0
cycle
11
Data3
cycle
12
CYNSE10512
CYNSE10256
CYNSE10128
Page 53 of 153
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