CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 113

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

The MSE bit in the Command Register must be set high to enable the MultiSearch feature. The same with the Enhanced Mode
(EMODE) bit. The following is the sequence of operation for a single mixed-width Search command (also refer to Subsection 6.2,
“Command Bus Parameters,” on page 50).
Note. For 72-bit multi-searches, the host ASIC can provide different 72-bit data on DQ[71:0] on each of the A and B cycles. The
even and odd pairs of GMRs selected for the comparison need not be programmed with the same value. For 144-bit, 288-bit or
576-bit searches, each 72-bit presented on each cycle A and B will together form the 144-bit or 288-bit or 576-bit search key
respectively. Each search key will be compared to both arrays 0 and 1 during cycles A and B when MultiSearch is enabled.
When an N-bit search key, K, is presented on the DQ bus, both arrays of N-bit entries are compared to the search key using the
GMR and local mask bits. The GMR is selected by the GMR Index in the command’s cycle A. K is also stored in both even and
odd comparand register pairs (selected by the comparand register index in command cycle B). K is compared with each entry in
the table, starting at location 0. A matching entry from each array that satisfies the Soft Priority and Mini-Key scheme will be the
winning entries, and their location addresses La and Lb will be driven as part of the SRAM address on the SADR[N:0] lines (see
Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128. Note. The
Learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than
one block.
The latency of the MultiSearch from command to SRAM access cycle is 5 for a configuration of up to eight devices (TLSZ = 01
(binary)). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
6.6
The device contains sixteen pairs of Comparand (CMPR) registers that store the search key as the device executes searches.
On a Search miss, signalled to the ASIC through the SSV and SSF signals (SSV = 1 (binary), SSF = 0 (binary)), the host ASIC
can apply the Learn command to learn the entry from a CMPR register to the next-free location. However, it is recommended that
the host ASIC first check the FULL signal, to determine if the device is full. If the device is not full, and the Search was a miss, a
Learn can be applied. If the device is already full, and the Learn is issued, the operation will be suppressed.
The Learn command is a pipelined operation and lasts for two CLK cycles. Figure 6-60, Figure 6-61 and Figure 6-62 show the
timing diagram of Learn operations with the address taken from the NFA or SRR register. Learn operations with the address taken
from the DQ bus follow the same diagrams except that the DQ bus contains the address instead of Don’t Cares. Figure 6-61 and
Figure 6-62 assume that the device performing the Learn operation is not the last device in the table and will therefore have its
LRAM bit set to 0. The OE_L for the device with the LRAM bit set goes HIGH for two cycles for each Learn (one during the SRAM
Write cycle and one during the cycle before). The SRAM Write cycle latency from the second cycle of the instruction is shown in
Table 6-13. The Learn command also generates a Write cycle to the external SRAM (see Section 6.7, “SRAM PIO Access,” on
page 121).
Note that mismatched entry-width Learn operation is not supported. For example, the result of a 72-bit Search miss stored in one
of the SRR registers cannot be used for a 144-bit Learn operation.
6.6.1
The Learn command in the Non-Enhanced mode supports x72 and x144 table widths. The operation uses the data stored in the
user selected CMPR register for writing to an entry in the Data array. Non-Enhanced mode Learn operation ignores the DQ bus
and cannot perform a write to the Mask array. The address for the target data entry is the INDEX field of the Next-free Address
(NFA) register.
Once the operation is completed the NFA register’s INDEX field is updated with next highest priority free entry in the Data array.
The LSB of each x72 entry is treated as a valid bit and used to indicate whether that entry is free (=0 (binary)) or not (=1 (binary)).
For a 144-bit entry, bit [72] and bit[0] must be set to the same value.
Document #: 38-02069 Rev. *F
• Cycle A:
• Cycle B:
— Command Bus: The host ASIC drives CMDV HIGH and applies Search command CMD[1:0] = “10” (binary). The CMD[2]
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10” (binary).
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
and CMD[9] signals must be driven to logic 0 for the 72-bit search, but for 144-bit search, CMD[9] = 1 and CMD [2] = 0.
For 288-bit search, CMD[9] is don’t care, whereas CMD[2] = 1 for the first “A” cycle and 0 for the last “A” cycle.
{CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this Search operation. CMD[7:6]
signals must be driven with the same bits that will be driven on SADR[24:23] for CYNSE10512, SADR[23:22] for
CYNSE10256, SADR[22:21] for CYNSE10128 by this device if it has a hit. CMD[8] must be set high for MultiSearch
operation.
CMD[5:2] must now be driven by the index of the comparand register pair for storing the search key presented on the DQ
bus during cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the
address of the matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
Learn Command
Non-Enhanced Mode
CONFIDENTIAL
PRELIMINARY
CYNSE10512
CYNSE10256
CYNSE10128
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