CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 29

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-5. Command Register Description (continued)
Document #: 38-02069 Rev. *F
EMODE
LRAM
CFGA
LDEV
HLAT
Field
MSE
BEN
LRN
EN
(decimal)
Range
[55:25]
[60:58]
[71:64]
[24:9]
[6:4]
[56]
[57]
[61]
[62]
[63]
[7]
[8]
Initial Value
(binary)
000
0
0
0
0
0
0
0
0
Latency of Hit Signals. This field adds latency to the SSF, SSV, FULL and MULTI_HIT
signals (in addition to the latency of TLSZ) during a Search operation and ACK signal during
SRAM Read accesses as listed below:
000: 0
001: 1
010: 2
011: 3
Last Device in the Cascade. When set, the device is the last device in a cascaded and is
the default driver for the SSF and SSV signals. In the event of a Search failure, the device
with this bit set drives the hit signals as follows: SSF = 0 (binary), SSV = 1 (binary). In an
operation other than Search, the device with this bit set drives the hit signals as follows: SSF
= 0 (binary), SSV = 0 (binary). When multiple devices are cascaded, one of the devices must
have LDEV set to 1.
Last Device on the SRAM Bus. When set to 1, this is the last device on the SRAM bus in
a cascade and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals.
In cycles where none of the Ayama 10000 devices in a cascade drive these signals, this
device drives the signals as follows:
For CYNSE10512: SADR = 0x1FFFFFF
For CYNSE10256: SADR = 0xFFFFFF
For CYNSE10128: SADR = 0x7FFFFF
For CYNSE10512/256/128:
CE_L = 1
WE_L = 1
ALE_L = 1
The device with this field set to 1 always drives OE_L. When multiple devices are cascaded,
one of the devices must have LRAM set to 1.
Database Configuration. The field is an alias for the first eight pairs of partition configuration
bits of the configuration register. Reading and writing this field is reflected in the configuration
register and vice versa. This field is only used when the device operates in the Non-Enhanced
mode.
Reserved.
DQ Bus Parity Enable. When set to 1, it enables parity checking on the data transferred
through DQ bus.
Core Parity Enable. When set to 1, it enables Core parity checking.
Reserved.
Enhanced LEARN Enable. When set to 1, it allows the user to select the data source for
the Learn operation from either the DQ bus or one of the CMPRs. It also allows the user to
select whether the write is to the data or the mask array. This field is valid in the Enhanced
mode.
MultiSearch Enable. When set to 1, it activates support for MultiSearch operation. The
SRAM output operates at CLK2X rate instead of CLK1X. This field is valid only when the
EMODE field of COMMAND register is set to 1.
Enhanced Mode. When set to 1, the device operates in the Enhanced mode. When cleared
to 0, the device operates in the Non-Enhanced mode.
Reserved.
CONFIDENTIAL
100: 4
101: 5
110: 6
111: 7
PRELIMINARY
Description
CYNSE10512
CYNSE10256
CYNSE10128
Page 29 of 153
[+] Feedback
[+] Feedback