CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 11

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

2.0
Cypress Semiconductor Corporation’s (Cypress’s) Ayama™ 10000 Network Search Engine (NSE) is designed to be a high-
performance, pipelined, synchronous, 512K/256K/128K 36-bit entries NSE. This high-speed, high-capacity Ayama 10000 NSE
can be deployed in a variety of networking and communications applications. It can be used to accelerate network protocols such
as Longest-Prefix Match (CIDR), ARP, MPLS, and other layer 2, 3, and 4 protocols. The performance and features of the
Ayama 10000 make it attractive in applications such as Enterprise LAN switches and routers, and broadband switching and/or
routing equipment that supports multiple data rates at OC–48 and beyond. Ayama 10000 can operate at a maximum performance
of 266 million searches per second (MSPS).
The Ayama 10000 is designed to be scalable in order to support network database sizes of up to 15872K 36-bit entries specifically
for environments that require large network policy databases. It includes features that ease table management, reduce power
consumption and improve data integrity. The device can have its features individually enabled or disabled for flexibility based on
the needs of the applications. The Ayama 10000’s Data and Mask arrays that make up the Core are organized into blocks that
can be individually configured to optimize the device performance and provide even more flexibility.
Figure 2-1 below shows the block diagram of the Ayama 10000.
Document #: 38-02069 Rev. *F
FULI[6:0]/LHI_1[6:0]
CLK1X/CLK2X
LHI[6:0]/LHI_0[6:0]
PARERR_L
CLK_MODE
CMD[10:0]
DQ[71:0]
PAR[1:0]
Overview
ID[4:0]
PHS_L
CMDV
RST_L
EOT
ACK
BHI[2:0]
FULL
PIO Access
Command
Decode
Parity
and
Full Logic
Figure 2-1. Ayama™ 10000 Block Diagram
CONFIDENTIAL
PRELIMINARY
CMD
Control and Configuration
Internal Registers
Block Associated
Internal Registers
Mask Array
Data Array
Compare / PIO Data
Arbitration
Logic
Controller
Interface
Control
Pipeline
SRAM
TAP
and
OE_L
CE_L
ALE_L
SADR[N:0],
WE_L
MULTI_HIT
FULO[1:0]/LHO_1[1:0]
LHO[1:0]/LHO_0[1:0]
BHO[2:0]
SSF
SSV
CYNSE10512
CYNSE10256
CYNSE10128
TMS
TCK
TRST_L
TDI
TDO
23 for
CYNSE10128
N = 25 for
CYNSE10512,
24 for
CYNSE10256,
Page 11 of 153
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