CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 44

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.9.1
The following table (Table 5-25) lists the parameters for addressing the Data array, Mask array and external SRAM.
Table 5-25. Data Array, Mask Array and External SRAM Address Space Encoding
The address generation of the SADR bits varies depending on the operation being performed. The following table (Table 5-26)
shows the SRAM address generation for the various operations.
Table 5-26. SRAM Address Generation
Document #: 38-02069 Rev. *F
Notes:
10. M = 17 for CYNSE10512; M = 16 for CYNSE10256; M = 15 for CYNSE10128.
12. SSR[2:0] is OR-ed with DQ[2:0] to generate the SADR[2:0] values.
ADDRESS
11. Non-Enhanced mode uses NFA register. Enhanced mode uses SRR register.
INDIRECT
9.
TARGET
PARITY
CHIPID
SRAM PIO Read
SRAM PIO Write
Field
SSR
Indirect Read
Indirect Write
When MultiSearch feature is enabled, SADR[M+8] is not used and SADR[M] will be 0 to indicate Array0 output or 1 to indicate Array 1 output.
Command
Search
Learn
Addressing the Data Array, Mask Array and External SRAM
71
(decimal)
Range
[20:19]
[25:21]
[28:26]
[71:31]
[N:0]
[29]
[30]
[M]
Figure 5-30. Data Array, Mask Array and External SRAM Address Space Encoding
63
SRAM Operation
Address. This field contains the location of the entry to be accessed on Direct Addressing operations.
N = 17 for CYNSE10512, 16 for CYNSE10256, 15 for CYNSE10128.
Note that on a burst Read or Write operation, the appropriate burst register (WBURADR or RBURADR)
INDEX field is used as the address.
Reserved. M = 18 for CYNSE10512, [18:17] for CYNSE10256, [18:16] for CYNSE10128.
Target Area Select. This field indicates in what context the access takes place. It is encoded as follows:
00: Access the Data array
01: Access the Mask array
10: Access the external SRAM
11: Access the Internal Registers (Refer toSection 5.9.2)
Device ID. This field indicates which NSE device should respond to the READ or WRITE operation.
CHIPID value “11111” indicates a broadcast operation.
SSR Index. This field selects the SSR for Indirect accesses.
Indirect Addressing Enable.
1: Indirect.
When DQ[30] is 0, the selected SSR register INDEX field is used to generate the address as follow:
{SSR[17:3], SSR[2] | DQ[2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
To issue a Read Parity command, this bit must be set to 1. The address of the entry location to be
checked is taken from the PARITY control register’s ADR field. Note that Read Parity command can
be issued only on a Read command. Issuing an Indirect Write with Bit[30] set to 1 will result in No-
Operation.
0: Direct. DQ[17:0] contains the address for the operation.
Read Parity. This bit must be set to 1 to issue a Read Parity command. It is valid only when DQ[29]
is also set to 1.
Reserved.
Read
Write
Read
Write
Read
Write
55
47
SADR[M+8:M+6]
CONFIDENTIAL
CMD[8:6]
CMD[8:6]
CMD[8:6]
CMD[8:6]
CMD[8:6]
CMD[8:6]
PRELIMINARY
39
[9]
SADR[M+5:M+1]
N = 16 for CYNSE10256
31
Description
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
CHIPID
23
15
N = 17 for CYNSE10512
SSR[M:0] | DQ[2:0]
SSR[M:0] | DQ[2:0]
N = 15 for CYNSE10128
NFA/SRR[M:0]
SADR[M:0]
ADDRESS
Index[M:0]
DQ[M:0]
DQ[M:0]
CYNSE10512
CYNSE10256
CYNSE10128
7
[9,10]
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