CYNSE10128-083FGCI CYPRESS [Cypress Semiconductor], CYNSE10128-083FGCI Datasheet - Page 58

• Manufacturer Part Number: CYNSE10128-083FGCI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Note. For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both cycles A and B. Also, the
even and odd pairs of GMRs selected for the comparison must be programmed with the same value. For 144-bit, 288-bit or 576-
bit searches, each 72-bit presented on each cycle A and B will together form the 144-bit or 288-bit or 576-bit search key
respectively.
When an N-bit search key, K, is presented on the DQ bus, the entire table of N-bit entries is compared to the search key using
the GMR and local mask bits. The GMR is selected by the GMR Index in the command’s cycle A. K is also stored in both even
and odd comparand register pairs (selected by the comparand register index in command cycle B). K is compared with each entry
in the table, starting at location 0. A matching entry that satisfies the Soft Priority and Mini-Key scheme (for Enhanced Mode) will
be the winning entry, and its location address L will be driven as part of the SRAM address on the SADR[N:0] lines (see
Section 6.7, “SRAM PIO Access,” on page 121), N = 25 for CYNSE10512, 24 for CYNSE10256, 23 for CYNSE10128.
The latency of the Search from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ[1:0] = 01). SSV
and SSF also shift further to the right for different values of HLAT, as specified in Table 6-5.
Figure 6-6 shows an example of multiple table configuration with a CYNSE10512 device.
Table 6-5. Shift of SSF and SSV from SADR
Referring to Figure 6-6, if the CYNSE10512 device is used in the Non-Enhanced Mode, the CFG field in the Configuration
Register should be configured to “1010101010101010010101010101010100000000000000000000000000000000” in order to
have three individual tables within a device. If the device is used in the Enhanced Mode, the NES field in the Block Mini-Key
Register (BMR) should be configured as follows:
6.5.2
The multiple search operates the search commands in parallel on the upper half (array 0) and lower half (array 1) of the data
array in the device. The results from the two parallel searches are then driven on the SRAM bus at twice that rate relative to
single-search. This subsection covers multi searches with a single device configured with tables of different widths (×72, ×144,
×288) in each of the two arrays. Figure 6-7 shows three sequential searches: first, a 72-bit Search on a ×72-configured table; a
144-bit Search on a ×144-configured table; and a 288-bit Search on a ×288-configured table.
Note: MultiSearch is only available in the Enhanced Mode, not in the Non-Enhanced Mode. Figure 6-8 shows the sample table.
One way to create multiple tables of different widths in an NSE is by having table designation bits. It is assumed that bits [71:70]
for each entry will be assigned such table designation bits. DQ[71:70] will be 00 in each of the two A and B cycles of the ×72-bit
MultiSearch (M-Search1). DQ[71:70] is 01 in each of the A and B cycles of the ×144-bit MultiSearch (M-Search2). DQ[71:70] is
10 in each of the A, B, C, and D cycles of the ×288-bit MultiSearch (M-Search3).
Document #: 38-02069 Rev. *F
• Cycle B:
• For the first 64 blocks in the data array, NES = 00 for 72-bit table width.
• For the next 32 blocks, NES = 01 for 144-bit table width.
• For the final 32 blocks, NES = 10 for 288-bit table width.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
must now be driven by the index of the comparand register pair for storing the search key presented on the DQ bus during
cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the
matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
HLAT (binary)
Mixed-size Multi Searches with One Device on Tables Configured with Different Widths
000
001
010
011
Figure 6-6. Multiwidth Configurations Using CYNSE10512 as an Example
Number of CLK Cycles
0
1
2
3
128K
16K
CONFIDENTIAL
32K
PRELIMINARY
72
144
288
HLAT
100
101
110
111
Number of CLK Cycles
CYNSE10512
CYNSE10256
CYNSE10128
4
5
6
7
Page 58 of 153
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