cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 91

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
100046D
7
6
5
4
3
2–0
Bit
1
1
1
1
1
3
Field
Size
Enable HEC
Alignment
Enable Parallel
Interface
External Framer
Disable B3ZS/HDB3
Unframed Input
PHY Type
Name
Enables cell delineation via the HEC alignment method. This method is for use in any
mode where cells are directly mapped into the physical layer. When this bit is set,
53-octet cells are expected. When this bit is low, 57-octet cells (with PLCP framing
overhead) are expected.
Selects the parallel interface for input/output. When this bit is low, serial data is
expected; when high, parallel data is expected.
Set if line framing is performed with an external framer. When this bit is low, the
internal framer for the selected mode will be used.
Bypasses the internal encoder/decoder so that NRZ data can be presented directly to
the internal framing functions. For E1 and DS1 in external framer mode, set to 0.
Specifies whether the serial stream from an external circuit contains overhead or
only payload. The normal mode is framed mode. Physical layer overhead bits are
located by a synchronization input and are ignored by the PHY framer. In unframed
mode, all line framing bit positions are assumed to be nonexistent.
Sets the type of line framing and physical processing to be used. PHY modes are
always symmetric; the transmit and receive modes are identical. The PLCPs for DS1
and DS3 are described in TR-TSV-000773; E1 and E3 PLCPs are described in ETSI
draft standards prETS 300 213 and prETS 300 214; E3, DS3, and E4 direct-mapped
modes are described in ITU G.832; and STS-1 and STS-3c formats are described in
TR-NWT-000253.
Conexant
Description
3.3 Configuration Control Registers
3.0 Registers
3-5