cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 101

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
0x60—DL_CTRL_STAT (HDLC Data Link Control and Status Register)
The DL_CTRL_STAT register is located at address 0x60. The eight LSBs of this register are control bits and
can be read or written. The eight MSBs are status bits and can only be read. Programming of the HDLC data
link is discussed in
100046D
15
14
13–11
10
9
8
7
6
5–3
2
1
0
Bit
1
1
3
1
1
1
1
1
3
1
1
1
Field
Size
Receiver Interrupt
Transmitter
Interrupt
RX Bytes[2:0]
Idle Code Received
Bad FCS
Abort Flag Received
Enable Receive Data
Link Interrupt
Disable Data Link
Transmission
TX Bytes[2:0]
Abort Message
Send FCS
Send Message
Section
Name
2.8.
Indicates that the receiver needs service. A read to DL_CTRL_STAT clears this
interrupt.
Indicates that the transmitter needs service. A write to DL_CTRL_STAT clears this
interrupt.
A 3-bit pointer to the last location written in the receive message buffer by the data
link receiver.
Indicates that an idle flag sequence (0111 1110) was received on the receive data
link.
Set when an erroneous Frame Check Sequence (FCS) was received at the end of a
message or an idle flag is received that is not byte aligned.
Set if an abort sequence (seven consecutive 1s) was received on the receive data
link.
Enables the receiver interrupt to appear on the DL_INT output pin.
Forces the data link bits to all 1s.
A 3-bit pointer to the transmit message buffer indicating the location of the last byte
to be transmitted.
Causes the data link transmitter to halt the message in progress, send an abort flag,
and then resume transmission of idle flags on the data link.
Controls the transmission of the FCS at the end of a message block.
Instructs the transmitter to begin transmission of a message block on the data link.
Setting this bit removes the data link from idle flag transmission mode and enables
transmitter interrupts to the controller for data bytes.
Conexant
Description
3.4 Transmit Control Registers
3.0 Registers
3-15