cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 103
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cn8223
Manufacturer Part Number
cn8223
Description
Atm Transmitter/receiver With Utopia Interface
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8223.pdf
(161 pages)
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CN8223
ATM Transmitter/Receiver with UTOPIA Interface
0x08—TX_RATE_23 (Transmit Rate Control Register)
The TX_RATE_23 register is located at address 0x08. Each 8-bit field controls the maximum transmission rate
for ports 3 or 2. These fields are used to control the percentage of the total line rate allocated to each of the four
FIFO transmit ports. Setting these fields to 0 stops transmission on the port. Setting to 0xFF allows the
maximum available rate. Transmit rate control is described in
0x09—TX_RATE_01 (Transmit Rate Control Register)
The TX_RATE_01 register is located at address 0x09. Each 8-bit field controls the maximum transmission rate
for ports 1 or 0. These fields are used to control the percentage of the total line rate allocated to each of the four
FIFO transmit ports. Setting these fields to 0 stops transmission on the port. Setting to 0xFF allows the
maximum available rate. Transmit rate control is described in
0x0A—TX_IDLE_12 (Transmit Idle Header Register)
The TX_IDLE_12 register is located at address 0x0A. This register sets the ATM idle cell header octets 1 and 2.
0x0B—TX_IDLE_34 (Transmit Idle Header Register)
The TX_IDLE_34 register is located at address 0x0B. This register sets the ATM idle cell header octets 3 and 4.
100046D
15–8
7–0
15–8
7–0
15–8
7–0
15–8
7–0
Bit
Bit
Bit
Bit
Field
Field
Field
Field
Size
Size
Size
Size
8
8
8
8
8
8
8
8
Rate Value-Port 3
Rate Value-Port 2
Rate Value-Port 1
Rate Value-Port 0
Header Octet 1
Header Octet 2
Header Octet 3
Header Octet 4
Name
Name
Name
Name
Maximum rate: 0x00 to 0xFF
Maximum rate: 0x00 to 0xFF
Normally written to 00.
Normally written to 00.
Normally written to 00.
Normally written to 01.
Conexant
Section
Section
Maximum rate: 0x00 to 0xFF
Maximum rate: 0x00 to 0xFF
Description
Description
Description
Description
2.7.3.
2.7.3.
3.4 Transmit Control Registers
3.0 Registers
3-17
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