cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 84

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.8 FEAC Channel and HDLC Data Link Programming
2-50
2.8.4.2 Receiver
Interrupts
used directly. It is important that software strategies allow for the fact that the
LAPD receiver cannot recognize the FCS as such until the closing flag is
recognized. It can happen that the processor is interrupted to read 4 message
bytes, and the next byte received is the closing flag.
pending for the end of message. The status for this interrupt indicates the idle
condition, the FCS status, and the byte count will be the same as the previous
interrupt (RxBytes[2:0] = 3 or 7) because no extra bytes were received. In this
event, the last two bytes read from memory on the previous interrupt were not
message bytes after all, but were actually the FCS bytes. If the FCS spans a 4-byte
boundary, the final interrupt indicates that one additional byte was received
(RxBytes[2:0] = 0 or 4), the idle condition, and the FCS status.
The data link receiver generates an interrupt in response to three events:
upon the reading of this register.
Code Received is cleared, and RxBytes[2:0] indicates which half of the buffer
must be read.
Received is set, Bad FCS indicates the result of the FCS error check, and
RxBytes[2:0] indicates the last location written. The processor is not interrupted
again until four bytes of a new message have been received.
set, and there is nothing to be done by software other than discard any previously
received message bytes. The processor will not be interrupted again until four
bytes of a new message have been received.
[bit 15] in DL_CTRL_STAT. Interrupts must be enabled to appear on DL_INT by
setting Enable Receive Data Link Interrupt [bit 7] in DL_CTRL_STAT.
Alternatively, the FCS data may be ignored, and the good or bad indication
When the processor exits the interrupt routine, another interrupt will be
1.
2.
3.
DL_CTRL_STAT indicates the cause of the interrupt. The interrupt is cleared
If the interrupt is due to the current half of the receive buffer being full, Idle
If the interrupt is due to the end-of-message flag being detected, Idle Code
If the interrupt is due to an abort flag being received, Abort Flag Received is
Interrupts from the HDLC data link receiver appear on Receiver Interrupt
The current half of the message buffer is full
The end-of-message flag was detected
An abort flag was detected
Conexant
ATM Transmitter/Receiver with UTOPIA Interface
100046D
CN8223