cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 111

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
0x2E—EN_EVENT_INT (Enable Event Interrupts)
The EN_EVENT_INT register is located at address 0x2E and enables interrupts for the EVENT_STATUS
register (0x39). Setting a bit in EN_EVENT_INT enables each interrupt condition to appear on STAT_INT.
100046D
15
14–13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Field
Size
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
Receiver Hold Input
Interrupt Enable
Reserved
APS Interrupt
Start of Cell Error
Port 3 Input Parity Error
Interrupt Enable
Port 2 Input Parity Error
Interrupt Enable
Port 1 Input Parity Error
Interrupt Enable
Port 0 Input Parity Error
Interrupt Enable
Idle Cells Interrupt Enable
Non-matching Cells
Interrupt Enable
Non-zero GFC Interrupt
Enable
Payload Length Error
Interrupt Enable
Payload CRC Error
Interrupt Enable
HEC Error Not Corrected
Interrupt Enable
HEC Error Corrected
Interrupt Enable
Name
Indicates that an active-high input was received on the RCV_HLD input pin.
Set to 0.
Enables interrupt when received value of the K1 or K2 byte changes in the
SONET frame.
Indicates that a Start of Cell Alignment Error was received on the
FCTRL_IN[0] input pin (109).
Enables parity error interrupt from FIFO data input port 3. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
Enables parity error interrupt from FIFO data input port 2. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
Enables parity error interrupt from FIFO data input port 1. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
Enables parity error interrupt from FIFO data input port 0. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
Enables interrupt when header of an incoming cell matches the header value
programmed in the RX_IDLE and IDLE_MSK registers.
Enables interrupt when the header of an incoming cell does not match any of
the header values programmed in the HDR_VALx and HDR_MSKx registers.
Enables interrupt when the 4-bit GFC field of an incoming cell header is any
value other than 0000.
Enables interrupt when an error is detected in the 6-bit payload length field of
the cell trailer. This event is meaningful only for AAL3/4 payloads that contain
a payload length.
Enables interrupt when an error is detected in the 10-bit payload CRC of the
cell trailer. This event is meaningful only for AAL3/4 payloads that contain a
payload CRC.
Enables interrupt when an uncorrectable error is detected in the HEC octet of
the cell header.
Enables interrupt when an error is detected and corrected in the HEC octet of
the cell header.
Conexant
Description
3.6 Interrupt Enable Control Registers
3.0 Registers
3-25