cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 20
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cn8223
Manufacturer Part Number
cn8223
Description
Atm Transmitter/receiver With Utopia Interface
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8223.pdf
(161 pages)
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1.0 Product Description
1.5 FIFO Port/UTOPIA Interface
Figure 1-4. FIFO Port/UTOPIA Interface Block
1.5.1 UTOPIA Mode
1.5.2 FIFO Ports
1-10
Processing
ATM Cell
Block
Rx VPI/VCI
Screening
1.5 FIFO Port/UTOPIA Interface
The CN8223 FIFO Port/UTOPIA interface is the data connection for the host
system.
modes for interfacing with ATM cells: four FIFO ports or one ATM Forum Level
1 Compliant UTOPIA port.
UTOPIA mode implements a single 25 MHz, 8-bit plus parity bidirectional
interface with four cells of internal FIFO in both directions. Parity is optional.
When the UTOPIA interface mode is used, only 53-octet output is available.
Cells are routed to one of four output ports if a match to that port’s programmable
header value is made. This can be used to route received VCI/VPIs to a chosen
port. Four modes are available for FIFO port cell output:
FIFO port/UTOPIA interface block features include the following:
• Four byte-wide FIFO ports
• UTOPIA port with four-cell buffer
• Port rate and priority control
• Idle cell TX/Rx
• Per-port ATM header screening
• 48-, 52-, 53-, and 57-octet cell modes
• A test mode writes the entire 57-octet PLCP slot to the FIFO interface.
• A 53-octet mode writes the 53-octet ATM cell to the FIFO interface.
• A 52-octet mode writes the ATM cell without the HEC octet to the FIFO
• A final mode delivers 48-octet cell payloads to the FIFO interface.
interface.
Figure 1-4
Interface
Interface
UTOPIA
Buffers
4-Port
4-Cell
FIFO
Data
and
illustrates the functions in this block. This block has two
UTOPIA Ctrl
Conexant
Port 0 Ctrl
Port 1 Ctrl
Port 2 Ctrl
Port 3 Ctrl
9
9
ATM Transmitter/Receiver with UTOPIA Interface
FCTRL_OUT[16:0]
FCTRL_IN[7:0]
FDAT_IN
FDAT_OUT
Cell Processing
ATM Layer
FIFO
100046D
CN8223
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