cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 90

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

3.0 Registers
3.3 Configuration Control Registers
3.3 Configuration Control Registers
0x00—CONFIG_1 (Configuration Control Register 1)
The CONFIG_1 register is located at address 0x00. This register sets chip parameters for both transmit and
receive operations. The line interface type is set for both transmit and receive by bits 7–0. Valid combinations of
bits 7–0 for the line interface type in this register are given in
3-4
15
14
13
12
11
10
9
8
Bit
1
1
1
1
1
1
1
1
Field
Size
STS-1 Stuffing
Option
Source Loopback
Enable One-Second
Latching of Line
Counters
Enable One-Second
Latching of Line
Status
External 8 kHz
Timing
Receiver Hold
Enable
Enable Cell
Scrambler
Disable LOCD
Name
Enables an alternate ATM mapping for STS-1 mode. If this bit is set, then 84
columns of the SPE are available for ATM cell octets. If this bit is not set, then all 86
columns of the SPE are available for ATM cell octets.
Causes the receiver input to be taken from the transmitter output in all modes; the
transmitter output is unaffected. This function allows the generation of
self-diagnostic routines at system startup to ensure the health of the line/physical
framing process. If an external framer mode is selected, the external framer needs to
continue providing an input to TXSYI when source loopback is enabled. Source
loopback does not work in TAXI mode.
Causes status indications in the line/PHY counters (other than LCV) to be latched at
one-second intervals. This interval is determined by successive rising clock edges to
ONESECI. If an alarm condition is present during a one-second interval, it is
available to be read on the successive interval. Otherwise, the status is latched and
held until it is read. If this bit is set and the status word is read twice within a
one-second interval, the second read gives the current state of the status word and
clears it.
Causes status indications in the LINE_STATUS register to be latched at one-second
intervals. The one-second interval is determined by successive rising clock edges to
ONESECI. If an alarm condition is present during a one-second interval, it is
available to be read on the successive interval. Otherwise, the status is latched and
held until it is read. If this bit is set and the status word is read twice within a
one-second interval, the second read gives the current state of the status word and
clears it.
Forces the transmit PLCP to be synchronized to an external 8 kHz timing reference
rather than to the received PLCP reference. This control bit is meaningful only in
57-octet DS3 and E3 formats.
Allows the RCV_HLD input to disable cell processing. Internal cell receiver functions
will operate, but no segments will be accepted by the cell validation state machine or
output on the FIFO ports.
Enables the x
payload.
Allows cell validation and error counting to continue when cell delineation is lost (via
either PLCP or HEC).
Conexant
43
+ 1 scrambler (required for 53-octet direct mapping) for cell
Table
ATM Transmitter/Receiver with UTOPIA Interface
3-3.
Description
CN8223
100046D