w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 86

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

register are cleared if the corresponding write data bits are '1' in a write operation.
all accesses except configuration accesses. The power up value of Command register is 00
.
Bit 31
Bit 30
Bits 29-28
Bit 27
Bits 26-25
Bits 24
Bit 23
Bit 22
Bit 21
Bit 20 CAP
Bits 19-16
Bits 15-10
Bits 9
Bits 31-16 are Status register and bits 15-0 are Command register. Reads to Status register behave normally. Bits in Status
Bits 15-0 are Command register. When 00
1 = A parity error is detected.
0 = No parity error is detected.
Not implemented. Read as 0.
Not implemented. Read as 0.
1 = Target Abort is signaled.
0 = Target Abort is not signaled.
01 = Medium DEVSEL# timing.
Not implemented. Read as 0.
0 = Unable to accept fast back-to-back transaction.
0 = Unable to support User Definable Features.
0 = Support 33 MHz only.
1 = Power management capability is supported.
Not implemented. Read as 0.
Fast Back-to-back
DPE
SSE
STA
FBT
UDF
66M
PERR# Asserted
Master Aborted, Target Aborted
DEVSEL Timing
Reserved
Reserved
Signaled System Error
Signaled Target Abort
Fast Back-to-back Transaction
66 MHz Function
Detected Parity Error
User Definable Features
Capability
Read as 0
Read as 0
Read_only
Read_only
Read_only
R/W_clr
H
R/W_clr
Read_only
is written to this register, the device is logically disconnected from the PCI bus for
Read_only
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W6692 PCI ISDN S/T-Controller
Publication Release Date:
H
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9