w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 24

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

clocks are turned off, but the analog level detector is still active to detect signal coming from the S interface. The power down
state is left either by non-INFO 0 signal from S interface or C/I command from microprocessor.
7.2.2 Receiver Clock Recovery And Timing Generation
a 7.68 MHz clock as reference. According to I.430, the transmit clock is normally delayed by 2 bit time from the receive clock.
The "total phase deviation from input to output" is -7% to +15% of a bit period. In some cases, delay compensation may be
needed to meet this requirement (see OPS1-0 bits in D_CTL register).
setting.
7.2.3 Layer 1 Activation/Deactivation
signals received at S interface or commands issued from microprocessor. The state outputs signals to S interface and indication to
microprocessor. The CIX register is used by microprocessor to issue command, and the CIR register is used by microprocessor to
receive indication.
single zero".
7.2.3.1 States Descriptions And Command/Indication Codes
F3 Deactivated without clock
reset, once the indication "1111" has been read out, internal clocks will turn off and stay at this state if INFO 0 is received on the
S line. The turn off time is approximate 93 ms. The ECK command must be issued to activate the clocks.
After hardware reset, the receiver may enter power down state in order to save power consumption. In this state, the internal
A Digital Phase Locked Loop (DPLL) circuit is used to derive the receive clock from the received data stream. This DPLL uses
The PCM output clocks (PFCK1-2, PBCK) are synchronous to the S-interface timing.
The layer 1 activation/deactivation procedures are implemented by a finite state machine. The state transitions are triggered by
Some commands are used for special purposes. They are "layer 1 reset", "analog loopback", "send continuous zeros" and "send
This is the "deactivated" state of ITU-T I.430. The receive line awake unit is active except during a hardware reset pulse. After
W6692 does not need RC filter on receiver side, therefore zero delay compensation is selected normally. This is the default
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE
OPS1
0
0
1
1
OPS0
0
1
0
1
Effect
No phase delay compensation
Phase delay compensation 260 ns
Phase delay compensation 520 ns
Phase delay compensation 1040 ns
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W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9