w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 25

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

F3 Deactivated with clock
command.
capacitances. (It is about 0.5 ms for 12pF to 33pF capacitance).
F3 Awaiting Deactivation
spurious effect on S interface. Any non-INFO 0 signal on the S interface causes transition to "F5 Identifying Input" state. If this
transition does not occur in a specific time (500 - 1000 ms), the microprocessor may issue DRC or ECK command to deactivate
layer 1.
F4 Awaiting Signal
0 is received from the S interface. The software starts timer T3 of I.430 when issuing activate request command. The software
deactivates layer 1 if no signal other than INFO 0 has been received on S interface before expiration of T3.
F5 Identifying Input
or INFO 4. This state is reached at most 50 s after a signal different from INFO 0 is present at the receiver of the S interface.
F6 Synchronized
state is reached at most 6 ms after an INFO 2 arrives at the S interface (in case the clocks were disabled in "F3 Deactivated
without clock").
F7 Activated
reached at most 0.5 ms after reception of INFO 4. From state "F3 Deactivated without clock" with the clocks disabled, state F7 is
reached at most 6 ms after the W6692 is directly activated by INFO 4.
F8 Lost Framing
deactivation by INFO 0.
Special States:
Analog Loop Initiated
line). The receiver is not yet synchronized.
Analog Loop Activated
sent depending on whether or not a signal different from INFO 0 is detected on the S interface.
This is the state where the W6692 has lost frame synchronization and is awaiting resynchronization by INFO 2 or INFO 4 or
The receiver is synchronized on INFO 3 which is looped back internally from the transmitter. The indication 'TI" or "ATI" is
When W6692 receives an activation signal (INFO 2), it responds with INFO 3 and waits for normal frames (INFO 4). This
This state is identical to "F3 Deactivated without clock" except the internal clocks are enabled. The state is entered by the ECK
The W6692 enters this state after receiving INFO 0 (in states F5 to F8) for 16ms (64 frames). This time constant prevents
This state is reached when an activate request command has been received. In this state, the layer 1 transmits INFO1 and INFO
After the receipt of any non-INFO 0 signal from NT, the W6692 ceases to transmit INFO 1 and awaits identification of INFO 2
This is the normal active state with the layer 1 protocol activated in both directions. From state "F6 Synchronized" , state F7 is
On Enable Analog Loop command, INFO 3 is sent by the line transmitter internally to the line receiver (INFO 0 is sent to the
The clocks are enabled approximately 0.5 ms to 4 ms after the ECK command, depending on the crystal
-25 -
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9