w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 44

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

comparisons can be selectively masked bit-by-bit via address mask registers. Comparison is disabled when the corresponding
mask bit is "1".
Bn_STAR: CRCE bit. The data between opening flag and CRC field (not included) is stored in receive FIFO. Two interrupts are
used for the reception of data. The RMR interrupt in Bn_EXIR register indicates at least a threshold block of data have been put
in the receive FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The micro-processor
can read out a threshold length of data from receive FIFO at RMR interrupt, or all the data in receive FIFO at RME interrupt. At
each RMR/ RME interrupt, micro-processor must issue a Receive Message Acknowledgement(RACK) command to explicitly
acknowledge the interrupt.
example, it is 8 ms if the FIFO threshold is 64 and the B channel data rate is 64 kbps.
and status bit.
time up to a threshold length of data has been stored in the FIFO, a Bn_RMR interrupt is generated.
generated.
7.7.2 Transmission of Frames in B Channel
receiver use the same FIFO threshold setting.
start the frame transmission, the microprocessor issues a XMS (Transmit Message Start) command. The transmitter requests
another block of data via XFR interrupt when more than a threshold length of vacancies are left in the FIFO.The micro-processor
then writes up to a threshold length of data into the FIFO and activates the subsequent transmission of the frame by a XMS
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt
The fields such as address, control and information are provided by the microprocessor and are stored in transmit FIFO. To
Transparent mode: The received frame address is compared with the contents in receive address registers. In addition, the
In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC check is indicated in
The microprocessor reaction time for RMR/ RME interrupt depends on the FIFO threshold setting and B channel data rate. For
Extended transparent mode: In this mode, all data received are stored in the receive FIFO without any modification. Every
In this mode, there is no RME interrupt.
A 128-byte FIFO is provided in the transmit direction. The FIFO threshold can be set at 64 or 96 bytes. The transmitter and
The transmit operations differ in both modes:
Transparent mode:
In this mode, the following functions are performed by the transmitter automatically:
The microprocessor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt and status bit will be
- Flag generation
- CRC generation
- Zero bit insertion
-44 -
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9