w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 43

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

interrupt.
command must be issued and software must wait until transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS
command to re-transmit the data.
7.7 B Channel HDLC Controller
- Transparent mode
7.7.1 Reception of Frames in B Channel
register. If the number of received data reaches the threshold, a Receive Message Ready (RMR) interrupt will be generated.
- Extended transparent mode
Collisions which occur on the D channel of S interface will cause an D_EXIR:XCOL interrupt. A XRST (Transmitter Reset)
After the microprocessor has issued the XME command, the successful termination of transmission is indicated by an D_XFR
The inter-frame time fill pattern must be all 1's, according to ITU-T I.430.
There are two B channel HDLC controllers. Each B channel HDLC controller provides two operation modes :
For PCM-HDLC connection, only extended transparent mode can be selected.
The data rate in B channel can be set at 64 kbps or 56 kbps by the B1_MODE (B2_MODE) : SW56 bit.
A 128-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 64 or 96 bytes by the Bn_MODE
The operations for reception of frames differ in each mode:
characteristics :
* 2 byte address field
* Receive address comparison maskable bit-by-bit
* Data between opening flag and CRC (not included) stored in receive FIFO
* Flag generation/ deletion
* Frame Check Sequence generation/ check with CRC_ITU-T polynominal
* Zero bit insertion/ deletion
characteristics :
* All data transmitted/ received without modification
* No address comparison
* No flag generation/ detection
* No FCS generation/ check
* No bit stuffing
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W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9