w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 58

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

XCOL
transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
TIN2
GCI
ISC
SQR registers.
T1EXP
.
8.1.9 D_ch Extended Interrupt Mask Register
Value after reset: FFH
zero. They are internally stored and pending until the mask bits are zero.
8.1.10 D_ch Status Register
Value after reset: 00H
XDOW
by XRST command.
XBZ
XDOW
At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten condition and is cleared only
RDOV
This bit indicates a collision on the S-bus has been detected. A XRST command must be issued and software must wait until
Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt status bits are read as
This bit is set when at least one bit is set in GCI_EXIR register.
A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be read from CIR or
Expiration occurs in the Timer 1.
All the interrupts in D_EXIR will be masked if the IMASK:D_EXI bit is set to "1".
This bit is set when Timer 2 counts down to zero.
7
7
Indication or S Channel Change
GCI Interrupt
Transmitter Busy
Timer 2 Expiration
Transmit Collision
XDUN
Timer 1 Expiration
Transmit Data Overwritten
6
6
XCOL
XBZ
5
5
DRDY
TIN2
4
4
D_XSTA
GCI
3
3
ISC
2
2
-58 -
D_EXIM
Read
T1EXP
1
1
0
1
0
Read/Write Address 20H/08H
Address 24H/09H
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9