w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 13

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

Pin
Name
CLK
AD31-AD0
C/BE3#-C/BE0#
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
RST#
INTA#
CLK
AD7-0
4. PIN DESCRIPTION
TABLE 4.1 W6692 PIN DESCRIPTIONS
Notation : The suffix "#" indicates an active LOW signal.
Pin
Number
84
85,86,87,90,91,
92,93,94,97,98,
99,100,7,8,9,10,
23,24,25,30,33,
34,35,36,38,39,
40,41,44,45,46,
47
95,11,22,37
21
12
14
13
18
15
96
19
81
80
84
38,39,40,41,44,45
,46,47
Intel Bus Mode (Selected when CLK=HIGH)
Type
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Functions
PCI Mode : PCI Clock. All other PCI signals, except RST#, INTA# are
sampled on the rising edge of CLK. According to PCI 2.1/2.2
specification, CLK is stable at least 100 s (Trst-clk) before deassertion
of RST#.
Intel Bus Mode : Must be pulled to HIGH.
Motorola Bus Mode : Must be pulled to LOW.
Address and Data are multiplexed on the same PCI pins. During the
address phase, AD31-0 contain a 32-bit physical address. During the
data phase, AD7-AD0 contain the least significant byte and AD31-
AD24 contain the most significant byte.
Bus command and Byte Enables.
During the address phase of a transaction, they define the bus
command.
During data phase, they are used as Byte Enables.
Parity is even parity across AD31-AD0 and C/BE3#-C/BE0#.
FRAME# is asserted to indicate a bus transaction is beginning.
Target Ready indicates W6692 is able to complete the current data
phase of the transaction.
Initiator Ready indicates the bus master s ability to complete the current
data phase of the transaction.
Stop indicates W6692 is requesting the master to stop the current
transaction.
Device Select indicates W6692 has decoded itself as the target of the
current access.
Initialization Device Select is used as chip select during configuration
transactions.
Parity Error is used for reporting of data parity errors.
PCI Reset. RST# may be asynchronous to CLK when asserted or
deasserted.
Interrupt. This is level sensitive, active LOW and open drain output.
This pin must be pulled to HIGH.
Multiplexed address and data. During the address phase, AD7-0 contain
a 8-bit physical address. During the data phase, AD7-AD0 contain data.
PCI Bus
-13 -
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Preliminary Data Sheet
Sep 30, 1999
Revision 0.9