w6692 Winbond Electronics Corp America, w6692 Datasheet - Page 62

• Manufacturer Part Number: w6692
• Description: Pci Bus Isdn S/t-controller
• Manufacturer: Winbond Electronics Corp America

8.1.19 D_ch Receive Frame Byte Count Low
Value after reset: 00H
RBC7-0
D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK
command.
8.1.20 Timer 2
Value after reset : 00H
TMD
count value.
changes to HIGH and toggles every half count time. Therefore, the period of TOUT2 equals count value.
TIDLE
TCN5-0
8.1.21 Layer 1_Ready Code
Value after reset: 0CH
RBC7
Eight least significant bits of the total frame length. Bits RBC5-0 also indicate the length of the data currently available in
TMD
In both cases, timer counts with the new value if it is written again before expiration.
The timer is stopped when it expires (TMD=0), or by writting zero count value (TMD=0 or 1).
This bit defines value of TOUT2 pin when timer if off.
In both cases, a maskable interrupt TIN2 is generated every time the timer reaches zero. When timer starts, pin TOUT2
1: Cyclic timer mode. The timer starts when it is written a non-zero count value and counts cyclically (periodically) with the
0: Timer is off.
1-63: Timer count value in unit of ms.
7
7
0: One shot count down mode. The timer starts when it is written a non-zero count value and stops when it reaches zero.
7
Timer 2 Mode
TIDLE
TOUT2 Idle
RBC6
Receive Byte Count
Timer 2 Count Value
6
6
6
RBC5
TCN5
5
5
5
RBC4
TCN4
TIMR2
4
4
4
RBC3
TCN3
L1_RC
RC3
3
3
3
RBC2
TCN2
RC2
2
2
2
Write
-62 -
D_RBCL
RBC1
TCN1
RC1
1
1
Read/Write
1
Address 4CH/13H
RBC0
TCN0
RC0
0
0
0
Read
W6692 PCI ISDN S/T-Controller
Publication Release Date:
Address 50H/14H
Preliminary Data Sheet
Address 48H/12H
Sep 30, 1999
Revision 0.9