mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 69

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

13.14
Address 014Dh
The Memory BIST register enables the built-in-self-test function for the on-chip memory testing. Two consecutive
write operations are required to start MBIST. The first with only Bit 12 (LV_TM) set High (i.e. 1000h), the second
with Bit 12 maintained High but with the required start bit(s) set High.
The MBISTR register is configured as follows:
15-13
Bit
12
11
10
9
8
7
6
5
4
Memory BIST Register
Reserved
BISTSDB
BISTCDB
BISTPDB
BISTSCB
BISTCCB
BISTSDL
BISTCDL
BISTPDL
LV_TM
Name
Table 48 - Backplane Output Bit Rate (BOBRR) Programming Table
Reset
0
0
0
0
0
0
0
0
0
0
Table 49 - Memory BIST Register (MBISTR) Bits
Reserved.
MBIST Test enable.
High for MBIST mode, Low for scan mode.
Backplane Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Backplane Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Backplane Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
BOBR1
0
0
1
1
BOBR0
Zarlink Semiconductor Inc.
0
1
0
1
MT90870
69
Bit rate for stream n
16Mb/s
Description
2Mb/s
4Mb/s
8Mb/s
Data Sheet