mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 24

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame
pulse with a single width frame pulse of 122 ns and the C8IPOL bit is set to one unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame pulse
(FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register bit,
COPOL. An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an
internal clock signal operated at 131.072 MHz.
2.4
The MT90870 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and
FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched.
Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s,
shows the backplane and local frame pulse alignment for different data rates.
For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 18,
Frame Boundary Conditions, ST- BUS Operation, and Figure 19, Frame Boundary Conditions, GCI - BUS
Operation.
3.0
3.1
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero
such that Ch0 is the first channel that appears after the frame boundary.
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s
Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
Input Channel Delay Programming (Backplane and Local Input Streams)
Input and Output Offset Programming
BSTi/BSTo0-31
BSTi/BSTo0-31
BSTi/BSTo0-31
BSTi/BSTo0-31
LSTi/LSTo0-15
LSTi/LSTo0-15
LSTi/LSTo0-15
LSTi/LSTo0-15
(16 Mb/s)
(16 Mb/s)
(2 Mb/s)
(4 Mb/s)
(8 Mb/s)
(2 Mb/s)
(4 Mb/s)
(8 Mb/s)
FP8o
FP8i
C8o
C8i
CH
CH
CH0
CH0
0
0
CH
CH
1
1
CH0
CH0
CH
CH
CH1
CH1
2
2
CH
CH
3
3
CH0
CH0
CH
CH
CH2
CH2
4
4
CH
CH
5
5
CH1
CH1
Zarlink Semiconductor Inc.
CH
CH
CH3
CH3
6
6
MT90870
CH
CH
7
7
and 16 Mb/s
CH
CH
CH4
CH4
8
8
24
CH
CH
9
9
CH2
CH2
CH
CH
10
CH5
10
CH5
CH
CH
11
11
CH1
CH1
CH
CH
12
CH6
12
CH6
CH
13
CH
13
CH3
CH3
CH
CH
14
14
CH7
CH7
CH
CH
15
15
CH
CH
16
16
CH8
CH8
CH
17
CH
CH4
CH4
17
CH
CH
18
18
CH9
CH9
CH
CH
19
19
CH2
CH2
CH
CH
20
20
CH10
CH10
CH
21
CH
CH5
CH5
21
CH
Data Sheet
CH
22
22
CH11
CH11
CH
CH
23
23