MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet
MT90870
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MT90870 Summary of contents
Page 1
... Scalable TDM-Based Architectures • Digital Loop Carriers Device Overview The MT90870 has two data ports, the Backplane and the Local port. The Backplane port has two modes of operation, either 32 input and 32 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination input and 16 output streams operated at 32 ...
Page 2
... Backplane Connection Memory Connection Memory (8,192 locations) (4,096 locations) Local Data Memories (4,096 channels) Microprocessor Interface and Internal Registers DS CS R/W A14-A0 DTA D15-D0 Figure 1 - MT90870 Functional Block Diagram Preliminary Information RESET ODE Local Interface Local Local Interface LSTo0-15 LCST0-1 ...
Page 3
... Preliminary Information The MT90870 is manufactured in a 27mm x 27mm body, 1.27mm ball-pitch, 272-PBGA to JEDEC standard MS-034 BAL-2 Iss corner identified by metallized marking Figure 2 - MT90870 PBGA Connections (272 PBGA) Pin Diagram (as viewed through top of package) MT90870 3 ...
Page 4
... MT90870 Pin Description Package Name Coordinates V D6, D11, D15, F4, DD_IO F17, K4, L17, R4, R17, U6, U10, U15 V A7, B4, B12, D14, DD_CORE K1, K20, N3, P18, T17, U16, V1, V5, Y7, Y11, Y14 V U12 DD_PLL V A1, D4, D8, D13, SS (GND) D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, ...
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... In 32Mb/s mode (stream rate 32Mb/s): BCSTo0 is the output enable for BSTo[0,4,8,12], BCSTo1 is the output enable for BSTo[1,5,9,13], BCSTo2 is the output enable for BSTo[2,6,10,14], BCSTo3 is the output enable for BSTo[3,7,11,15]. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state. MT90870 5 ...
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... MT90870 Pin Description (continued) Package Name Coordinates FP8i U14 C8i W12 CS B11 DS A11 R/W C11 A0 - A14 D5, C6, A6, D7, C7, B7, C8, B8, A8, D9, B9, A9, D10, C10, A10 D0 - D15 V10, Y9, W9, V9, U9, Y8, W8, V8, W7, V7, U7, Y6, W6, V6, Y5, W5 DTA A13 TMS D12 TCK A14 TDI B13 ...
Page 7
... Active high output enable: used to control per-channel basis, the external buffering of Local output streams . LCSTo0 is the output enable for streams: LSTo[0,2,4,6,8,10,12, and 14]. LCSTo1 is the output enable for streams: LSTo[1,3,5,7,9,11,13, and 15]. Refer to descriptions of the LORS and ODE pins for control of the output High or High-Impedance state. MT90870 7 ...
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... MT90870 Pin Description (continued) Package Name Coordinates ODE A12 BORS K2 LORS K19 NC A16, B16, Y12, Y13, 8 Description Output Drive Enable (5V Tolerant, Internal pull-up). An asynchronous input providing Output Enable control to the BSTo0- 31, LSTo0-15, BCSTo0-3 and LCSTo0-1 outputs. When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high impedance (dependent on the BORS and LORS pin settings respectively) and the outputs BCSTo0-3 and LCSTo0-1 are driven low ...
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... T18, T19, T20, U18, U19, U20, V17, V18, V19, V20, W18, W19, Y20, Y17, Y18, Y19, F18, F19, F20, G17, G18, G19, G20, H18, H19, H20, J17, J18, J19, J20, K17, K18 Description Internal Connects These inputs MUST be held LOW. MT90870 9 ...
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... Backplane input to Local output switching. Often a system design does not need to differentiate between Backplane and Local side, and merely needs maximum switching capacity. In this case, the MT90870 can be used as shown in Figure 4 to give the full 12,288 x 12,288 channel capacity. ...
Page 11
... The timing of the input and output clocks and frame pulses are shown in Figure 5, Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates. 2.2.1.1 Local Input Port The bit rate for each input stream is selected by writing to a dedicated Local Input Bit Rate Register (LIBRR0- 15). Refer to Table 41, Local Input Bit Rate Register (LIBRRn) Bits. MT90870 11 ...
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... MT90870 Stream Number Input stream - Backplane 0-15 (BSTi0-15) Input stream - Backplane 16-31 (BSTi16-31) Output stream - Backplane 0-15 (BSTo0-15) Output stream - Backplane 16-31 (BSTo16-31) Input stream - Local 0-15 (LSTi0-15) Output stream - Local 0-15 (LSTo0-15) Table 1 - Per-stream Data-Rate Selection: Backplane and Local, Non-32Mb/s Mode and 32Mb/s Mode FP8i (ST-BUS) ...
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... High-impedance state is controlled by the BE bit of the Backplane Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section 6.2, Backplane Connection Memory and Section 12.4, Backplane Connection Memory Bit Definition. MT90870 13 ...
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... MT90870 FP8i (ST-BUS) (8kHz) C8i (ST-BUS) (8.192MHz) FP8i (GCI) (8kHz) C8i (GCI) (8.192MHz) Channel 0 BSTi/BSTo0- (32Mb/s) ST Channel 0 BSTi/BSTo0- (32Mb/s) GCI BSTi/BSTo0- (16Mb/s) ST BSTi/BSTo0- (16Mb/s) GCI BSTi/BSTo0- (8Mb/s) ST BSTi/BSTo0- (8Mb/s) GCI BSTi/BSTo0-31 ...
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... Local Port Timing Diagram for 2,4,8 and 16Mb/s stream rates, and Figure 6, Backplane Port Timing Diagram for and 32Mb/s stream rates. The MT90870 will automatically detect whether an ST-BUS or a GCI- BUS style frame pulse is being used for the master frame pulse (FP8i). The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL ...
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... MT90870 3.0 Input and Output Offset Programming 3.1 Input Channel Delay Programming (Backplane and Local Input Streams) Various registers are used to control the input sampling point (delay) and the output advancement for the Local and Backplane streams. The following sections explain the details of these offset programming features. ...
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... Bit Delay, 3/4 Ch255 Ch0 Bit Delay, 1 Ch0 Ch255 Ch255 MT90870 Ch1 Ch1 Ch1 Ch1 Ch1 3 ...
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... MT90870 FP8o C8o Ch127 BSTi0-31/LSTi0- Bit Delay = 0 (Default) Ch127 BSTi0-31/LSTi0- Bit Delay = 1/4 Ch127 BSTi0-31/LSTi0-15 3 Bit Delay = 1/2 Ch127 BSTi0-31/LSTi0-15 3 Bit Delay = 3/4 Ch127 BSTi0-31/LSTi0-15 3 Bit Delay = 1 Ch126 BSTi0-31/LSTi0-15 2 Bit Delay = 7 1/2 Ch126 BSTi0-31/LSTi0-15 2 Bit Delay = 7 ...
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... Figure 11 - Backplane and Local Output Advancement Timing diagram for Data Rate of 16Mb/s Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Ch255 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 MT90870 Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Bit 4 Bit 4 ...
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... The input pin, LORS, selects whether the Local output streams, LSTo0-15 are set to high impedance at the output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the LCSTo0-1 signals ...
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... The Local Output Enable Bit (LE) of the Local Connection Memory has direcect per-channel control on the high-impedance state of the Local Output streams, LSTo0-15. Programming the LE bit to a LOW state will set the stream output of the MT90870 to High Impedance for the duration of the channel period. See Section 12.3, Local Connection Memory Bit Definition, for programming details. ...
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... MT90870 Allocated Stream No. C16o LCSTo0 1 Period 2041 4 2042 6 2043 8 2044 10 2045 12 2046 14 2047 0 2048 etc etc Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams (continued) Note 1: Clock Period count is referenced to Frame Boundary. Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. ...
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... Figure 12 - Local Port External High Impedance Control Bit Timing (ST-Bus mode Chan 0 Chan 0 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 MT90870 Channel 255 bits 7 Chan 127 Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 ...
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... The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at the output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-3 signals ...
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... etc etc etc etc MT90870 2 4Mb/s 2Mb ...
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... MT90870 FP8o C8o Channel 0 BSTo0 (16Mb/s) Chan 0 Chan 127 Chan 0 BSTo1 Bit 7 Bit 0 Bit 6 (8Mb/s) Chan 63 BSTo6 Bit 0 Chan 0 Bit 7 (4Mb/s) Chan 31 BSTo7 Bit 0 Channel 0 Bit 7 (2Mb/s) BCSTo0 BCSTo1 BCSTo2 BCSTo3 Figure 13 - Backplane Port External High Impedance Control Bit Timing (Non-32Mb/s mode) ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode). Allocated Stream No. BCSTo1 BCSTo2 BCSTo3 3 3-2 3-2 3-2 3 MT90870 2 Channel No. 32Mb/s Ch 511 Ch 511 Ch 511 Ch 511 Frame 27 ...
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... MT90870 C16o BCSTo0 1 Period etc etc 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 etc Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode). ...
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... Backplane Output streams, BSTo0-31 (for Non-32MB/s Mode) and BSTo0-15 (for 32Mb/s Mode). Programming the BE bit to a LOW state will set the stream output of the MT90870 to High Impedance for the duration of the channel period. See Section 12.4, Backplane Connection Memory Bit Definition, for programming details ...
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... Each data memory location corresponds to an input stream and channel number. To provide constant delay and maintain frame integrity, the MT90870 utilizes four pages of data memory. Consecutive frames are written in turn to each page of memory. Reading is controlled to allow a channel data written in frame read during frame N+3 ...
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... Preliminary Information 6.0 Connection Memory Description The MT90870 incorporates two connection memories, Local Connection Memory and Backplane Connection Memory. 6.1 Local Connection Memory The Local Connection Memory (LCM) is 16-bit wide with 4,096 memory locations to support the Local output port. The most significant bit of each word, bit [15], selects the source stream from either the Backplane or the Local port and determines the Backplane-to-Local or Local-to-Local data routing ...
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... MT90870 The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection Memory for the Write and Read operations via the microprocessor port. Microprocessor Port, and Section 13.1, Control Register (CR) for details on microprocessor port access. 6.3 Connection Memory Block Programming This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power up ...
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... Reset The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90870 synchronized to the internal clock and remains active for 50us following release (set HIGH) of the external RESET to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins LORS and BORS, the output streams LSTo0-15 and BSTo0-31 are set to high or high impedance, and all internal registers and counters are reset to the default state ...
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... MT90870 9.0 Bit Error Rate Test Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to allow either looped back, or uni-directional testing. The transmitter generates a 2 Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream and a number of channels ...
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... V when not driven from an external source. DD_IO 11.2 TAP Registers The MT90870 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction Register and three Test Data Registers. when not driven from an external source. DD_IO MT90870 when not ...
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... The Bypass Register The Bypass register is a single stage shift register to provide a one-bit path from TDI to TDO. 11.2.2.3 The Device Identification Register The JTAG device ID for the MT90870 is 0087014B Version, Bits <31:28>: 0000 Part No., Bits <27:12>: 0000 1000 0111 0000 Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit < ...
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... The address bits of the microprocessor define the addresses of the streams and the channels. The LDM is configured as follows: Bit Name 15-8 Reserved Set to a default value of 0 7-0 LDM Local Data Memory Local Input Channel Data Table 10 - Local Data Memory (LDM) Bits Description Description Description MT90870 37 ...
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... MT90870 12.3 Local Connection Memory Bit Definition The Local Connection Memory (LCM) has 4,096 addresses of 16-bit words. Each address, accessed through bits A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition for each 16-bit word is presented in Table 11 for Local-to-Local and Backplane(Non-32MB/s Mode)- to-Local connections, and in Table 12, for Local-to-Local and Backplane(32Mb/s Mode)-to-Local connections ...
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... Ignored when BMM is set HIGH. 8-0 BCAB8-0 Source Channel Address Bits. The binary value of these 9 bits represents the input channel number, when BMM is LOW.Bits BCAB7-0 transmitted as data when BMM is set HIGH. Table 14 - BCM Bits for Backplane-to-Backplane Switching (32Mb/s mode) Description Mode) Description MT90870 39 ...
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... MT90870 12.5 Internal Register Mappings A14 - A0 0000 Control Register 0001 Block Programming Register, BPR H 0002 BER Control Register, BERCR H 0003 0012 Local Input Channel Delay Register 0, LCDR0 - Register 15, LCDR15 0023 0032 Local Input Bit Delay Register 0, LIDR0 - Register 15, LIDR15 0043 ...
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... Local Data Memory is selected for Read-only operation. 011, Backplane Data Memory is selected for Read-only operation. Description ODE Pin OSB bit BSTo0 - 31, LSTo0 - Output Control with ODE pin and OSB bit Table 16 - Control Register Bits MT90870 Disable Disable Enable 41 ...
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... MT90870 (a) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b (b) Frame Pulse Width = 122ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b (c) Frame Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL ...
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... Control Register Bit6 (C8IPOL C8i_b FP8i_b (g) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b (h) Pulse Width = 244ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i_b FP8i_b Figure 18 - Frame Boundary Conditions, GCI - BUS Operation Frame Boundary MT90870 43 ...
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... MT90870 13.2 Block Programming Register (BPR) Address 0001h. The block programming register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must be defined in the same write operation. ...
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... A LOW to HIGH transition initializes the Local BER generator to the seed value. Clear Bit Error Rate Register for Local. A LOW to HIGH transition resets the Local internal bit error counter and the Local bit error (LBERR) register to zero. MT90870 selected for the ...
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... MT90870 Bit Name RESET 2 SBERRXL 0 1 SBERTXL 0 0 PRBSL 0 Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued) 13.4 Local Input Channel Delay Registers (LCDR0 to LCDR15) Address 0003h to 0012h. Sixteen Local input channel delay registers (LCDR0 to LCDR15) allow users to program the input channel delay for the Local input data streams LSTi0-15 ...
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... Table 20 - Local Input Channel Delay Programming Table Corresponding Input Stream Channel Delay LCD7-LCD0 1 Channel 2 Channels 3 Channels 4 Channels 5 Channels ... ... 253 Channels 254 Channels 255 Channels MT90870 Delay Bits 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 ... ... 1111 1101 1111 1110 1111 1111 47 ...
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... MT90870 13.5 Local Input Bit Delay Registers (LIDR0 to LIDR15) Address 0023h to 0032h. Sixteen Local input delay registers (LIDR0 to LIDR15) allow users to program the input bit delay for the Local input data streams LSTi0-15. The possible adjustment 3/4 of the data rate, advancing forward with a resolution of 1/4 of the data rate ...
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... Name Reset Reserved 0 Reserved BCD(8:0) 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream MT90870 LID1 LID0 ...
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... MT90870 13.6.1 Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0) These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the Backplane stream input pins. The input channel delay can be set to 511 (32Mb/s streams), 255 (16Mb/s streams), 127 (8Mb/s streams), 63 (4Mb/s streams (2Mb/s streams) from the frame boundary. ...
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... MT90870 Description 3 / BID1 BID0 bit 4 51 ...
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... MT90870 Data Rate 3 3 1/4 4 1 1/4 5 1 1/4 6 1 1/4 7 1/2 7 3/4 Table 26 - Backplane Input Bit Delay Programming Table (continued) 52 Corresponding Delay Bits (continued) BID4 BID3 BID2 ...
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... When the advancement is 0, the serial output stream has the normal alignment with the Local frame pulse. Local Output Advancement Clock Rate 131.072MHz 0 (Default) -2 cycle -4 cycles -6 cycles Table 28 - Local Output Advancement (LOAR) Programming Table Reset Description 0 Reserved 0 Local Output Advancement Register Corresponding Advancement Bits LOA1 MT90870 LOA0 ...
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... MT90870 13.9 Backplane Output Advancement Registers (BOAR0 - 31) Address 00A3h to 00C2h Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output advancement for output data streams BSTo0 to BSTo31. For 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s stream operation the possible adjustment is - cycles of the internal system clock (131.072MHz). For 32Mb/ s stream operation the possible adjustment is - cycles of the internal system clock (131 ...
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... The binary value of these bits refers to the Local output stream which carries the BER data. 0 Local BER Send Channel Address Bits. The binary value of these bits refers to the Local output channel in which the BER data starts to be sent. Description MT90870 Description 55 ...
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... MT90870 13.10.3 Local Receive BER Length Register (LRXBLR) Address 00C5h Local BER Receive Length Register (LRXBLR) defines how many channels the BER sequence will be received during each frame. The LRXBLR register is configured as follows: Bit Name Reset 15-8 Reserved 0 7-0 LRXBL(7:0) 0 Table 33 - Local Receive BER Length Register (LRXBLR) Bits 13 ...
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... Backplane BER Send Stream Address Bits The binary value of these bits define the Backplane output stream to transmit the BER data. Backplane BER Send Channel Address Bits The binary value of these bits define the Backplane output Start Channel in which the BER data is transmitted. Description MT90870 57 ...
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... MT90870 13.11.3 Backplane Receive BER Length Register (BRXBLR) Address 00CAh Backplane Receive BER Length Register (BRXBLR) defines how many channels in each frame the BER sequence will be transmitted. The BRXBLR register is configured as follows: Bit Name Reset 15-9 Reserved 0 8-0 BRXBL(8:0) 0 Table 38 - Backplane Receive BER Length (BRXBLR) Bits 13 ...
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... Reserved 0 Local Input Bit Rate LIBR0 Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s Reset 0 Reserved 0 Local Output Bit Rate LOBR1 LOBR0 Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s MT90870 Description Description 59 ...
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... MT90870 13.13 Backplane Bit Rate Registers 13.13.1 Backplane Input Bit Rate Registers (BIBRR0-31) Address 010Dh to 012Ch Thirty-two Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set Mb/s. These registers may be overridden by setting 32Mb/s mode in the control register, in which case, Backplane streams 0-15 will operate at 32Mb/s and Backplane streams 16-31 will be unused ...
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... Backplane Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence. A LOW indicates Pass, a HIGH indicates Fail. Table 49 - Memory BIST Register (MBISTR) Bits BOBR0 Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s Description MT90870 61 ...
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... MT90870 Bit Name Reset 2 BISTSCL 0 Local Connection Memory Start BIST sequence. Sequence enabled on LOW to HIGH transition. 1 BISTCCL 0 Local Connection Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. 0 BISTPCL 0 Local Connection Memory Pass/Fail Bit (Read only). This bit indicates the Pass/Fail status following completion of the Memory BIST sequence ...
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... Voltages are with respect to ground (V SS Symbol V DD_IO V DD_CORE V DD_PLL I_5V Sym Min T - 3.0 DD_IO V 1.62 DD_CORE V 1.62 DD_PLL I_5V ) unless otherwise stated. MT90870 Min Max Units -0.5 5.0 V -0.5 2.5 V -0.5 2.5 V -0.5 V +0.5 V DD_IO -0.5 7 ° +125 Typ Max Units °C 25 +85 3.3 3.6 V 1.8 1 ...
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... MT90870 DC Electrical Parameters Characteristics 1 Supply Current I Supply Current N 2 Input High Voltage P 3 Input Low Voltage U Input Leakage (input pins) Input Leakage (bi-directional pins Weak Pullup Current S 5 Weak Pulldown Current 6 Input Pin Capacitance 7 O Output High Voltage U 8 Output Low Voltage ...
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... LCP8 t 61 LCH8 t 61 LCL8 rLC8o fLC8o t 61 FPW16 t -30.5 FODF16 t 30.5 FODR16 t 61 LCP16 t 30 LCH16 t 30 LCL16 rLC16o fLC16o MT90870 Units Notes ns C =30pF =30pF =30pF =30pF =30pF ...
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... MT90870 FP8i (244ns) t BFPS244 FP8i (122ns) t BCL8 C8i CK_int * FP8o (244ns) FP8o (122ns) t LCL8 C8o FP16o t t LCL16 LCH16 C16o * CK_int is the internal clock signal of 131.072MHz Figure 19 - Backplane and Local Clock Timing Diagram for ST-BUS 66 t BFPW244 t BFPH244 t BFPW122 t t BFPS122 ...
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... CK_int is the internal clock signal of 131.072MHz Figure 20 - Backplane and Local Clock Timing for GCI-BUS t BGFPW t t BGFPS BGFPH t BCP8 t t BCH8 BCL8 t t fBCi t LFBOS t GFPW8 t t GFPS8o GFPH8o t t LCH8 LCP8 t FPW16 t FRH16o t LCP16 t rLC16o MT90870 rBCi t t rLC8o fLC8o t fLC16o 67 ...
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... MT90870 Backplane Data Timing Characteristic 1 Backplane Input data sampling point 2 Backplane Serial Input Set-up Time 3 Backplane Serial Input Hold Time 4 Backplane Serial Output Delay FP8i C8i CK_int * BSTi0 - 8.192Mb/s BSTo0 - 31 Bit1 Bit0 8.192Mb/s Ch127 Ch127 BSTi0 - 31 Bit0 Ch63 4.096Mb/s BSTo0 - 31 ...
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... BSIH32 BSOD32 Bit7 Bit6 Bit5 Bit0 Ch0 Ch0 Ch511 Ch0 t BIDS16 t BSIS16 t BSIH16 Bit0 Bit7 Ch0 Ch 255 t BSOD16 Bit0 Bit7 Ch255 Ch0 MT90870 Bit2 Bit4 Bit3 Ch0 Ch0 Ch0 Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 69 ...
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... MT90870 FP8i C8i CK_int * BSTi0 - 8.192Mb/s BSTo0 - 31 Bit1 Bit0 Ch127 Ch127 8.192Mb/s BSTi0 - 31 Bit0 Ch63 4.096Mb/s BSTo0 - 31 Bit0 Ch63 4.096Mb/s BSTi0 - 31 Bit0 Ch31 2.048Mb/s BSTo0 - 31 Bit0 Ch31 2.048Mb/s * CK_int is the internal clock signal of 131.072MHz Figure 23 - GCI BUS Backplane Data Timing Diagram (8Mb/s, 4Mb/s, 2Mb/s) ...
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... LSIS8 t 5 LSIS4 t 5 LSIS2 t 5 LSIH16 t 5 LSIH8 t 5 LSIH4 t 5 LSIH2 t LSOD16 t LSOD8 t LSOD4 t LSOD2 MT90870 Bit5 Bit4 Bit2 Bit3 Ch0 Ch0 Ch0 Ch0 Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 Typ Max Units Notes 7 =30pF ...
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... MT90870 FP8i C8i CK_int * LSTi0 - 15 Bit1 16.384Mb/s Ch 255 LSTo0 - 15 16.384Mb/s * CK_int is the internal clock signal of 131.072MHz Figure 25 - ST-BUS Local Timing Diagram (16Mb/ LFBOS t LIDS16 t LSIS16 t LSIH16 Bit0 Bit7 Ch 255 LSOD16 Bit0 Bit7 Ch255 Ch0 Preliminary Information Bit5 Bit6 ...
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... Bit7 Ch0 Sym Min Typ Max ODE t 13 ODZ , with timing corrected to cancel time taken to discharge C L MT90870 Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit6 Ch0 Bit6 ...
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... MT90870 Non-Multiplexed Microprocessor Port Timing Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS rising 7 Data setup from DTA Low on Read 8 Data hold on read 9 Data setup on write (fast write) ...
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... CS R/W A0-A14 D0-D15 READ D0-D15 WRITE DTA Figure 29 - Motorola Non-Multiplexed Bus Timing t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD MT90870 CSH RWH ADH DHR DHW AKH ...
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... MT90870 14.0 Package and Pin Information The MT90870 is available in a 272-PBGA (Plastic Ball Grid Array) package, body size 27mm x 27mm with 1.27mm ball-pitch. The assembly incorporates a centered 4x4 array of grounded balls for thermal management. The MT90870 272-PBGA (Plastic Ball Grid Array) Package ...
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