mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 61

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mt90870ag2

Manufacturer Part Number
mt90870ag2
Description
Flexible 12 K Digital Switch F12kdx
Manufacturer
Zarlink Semiconductor
Datasheet

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Table 26 illustrates the bit delay selection.
13.8
Address 0083h to 0092h.
Sixteen Local output advancement registers (LOAR0 to LOAR15) allow users to program the output advancement
for output data streams LSTo0 to LSTo15. The possible adjustment is -2, -4 or -6 cycles of the internal system clock
(131.072 MHz).
Local Output Advancement Registers (LOAR0 to LOAR15)
0 (Default)
Data Rate
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
7 1/4
7 1/2
7 3/4
1/4
1/2
3/4
1
2
3
4
5
6
7
Table 26 - Backplane Input Bit Delay Programming Table
BID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Zarlink Semiconductor Inc.
BID3
MT90870
Corresponding Delay Bits
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
61
BID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Sheet

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