mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 64

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

13.10.3
Address 00C5h
Local BER Receive Length Register (LRXBLR) defines how many channels the BER sequence will be received
during each frame. The LRXBLR register is configured as follows:
13.10.4
Address 00C6h
Local BER Start Receive Register defines the Input Stream and Start Channel and the stream in which the BER
sequence shall be received. The LBSRR register is configured as follows:
7-0
Bit
15-12
15-8
11-8
7-0
7-0
Bit
Bit
LTXBL(7:0)
Local BER Start Receive Register (LBSRR)
Name
Local Receive BER Length Register (LRXBLR)
LRXBL(7:0)
LBRSA(3:0)
LBRCA(7:0)
Reserved
Reserved
Name
Name
Table 32 - Local Transmit BER Length Register (LTXBLR) Bits
Table 33 - Local Receive BER Length Register (LRXBLR) Bits
Reset
Table 34 - Local BER Start Receive Register (LBSRR) Bits
0
Reset
Reset
0
0
Local Transmit BER Length Bits
The binary value of these bits define the number of channels in addition to the
Start Channel that the BER data will be transmitted on. (i.e. Total Channels =
Start Channel + LTXBL value)
0
0
0
Reserved.
Local Receive BER Length Bits
The binary value of these bits define the number of channels in addition to
the Start Channel allocated for the BER receiver. (i.e. Total Channels =
Start Channel + LRXBL value)
Reserved.
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream to receive
the BER data.
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input channel in which
the BER data starts to be compared.
Zarlink Semiconductor Inc.
MT90870
64
Description
Description
Description
Data Sheet