mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 15

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
D0 - D15
DTA
TMS
TCK
TDi
TDo
TRST
RESET
LSTi0-15
C16o
C8o
Name
V10, Y9, W9, V9,
U9, Y8, W8, V8,
W7, V7, U7, Y6,
W6, V6, Y5, W5
A13
D12
A14
B13
C13
B14
C12
L18, L19, L20,
M17, M18,
M19, M20, N18,
N19, N20, P17,
P19, P20, R18,
R19, R20,
W13
V13
Coordinates
Package
Data Bus 0 - 15 (5 V Tolerant). These pins form the 16-bit data bus of the
microprocessor port. (Data D0 = LSB).
Data Transfer Acknowledgment (5 V Tolerant). This active low output
indicates that a data bus transfer is complete. A pull-up resistor is
required to hold a HIGH level. (Max. I
Test Mode Select (5 V Tolerant with internal pull-up). JTAG signal that
controls the state transitions of the TAP controller.
Test Clock (5 V Tolerant). Provides the clock to the JTAG test logic.
Test Serial Data In (5 V Tolerant with internal pull-up). JTAG serial test
instructions and data are shifted in on this pin.
Test Serial Data Out (5 V Tolerant Three-state Output). JTAG serial
data is output on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG is not enabled.
Test Reset (5 V Tolerant with internal pull-up) Asynchronously
initializes the JTAG TAP controller to the Test-Logic-Reset state. To be
pulsed low during power-up for JTAG testing. This pin must be held LOW
for normal functional operation of the device.
Device Reset (5 V Tolerant with internal pull-up). This input (active
LOW) asynchronously applies reset and synchronously releases reset to
the device. In the reset state, the outputs LSTo0 - 15 and BSTo0 - 31 are
set to a high or high impedance depending on the state of the LORS and
BORS external control pins, respectively. It clears the device registers
and internal counters. This pin must stay low for more than 2 cycles of
input clock C8i for the reset to be invoked.
Local Serial Input Streams 0 to 15 (5 V Tolerant with internal pull-
down). These pins accept serial TDM data streams at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048 Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o Output Clock (Three-state Output). A 16.384 MHz clock output.
The clock falling edge or rising edge is aligned with the Local frame
boundary, this is controlled by the COPOL bit of the Control Register.
C8o Output Clock (Three-state Output). A 8.192 MHz clock output. The
clock falling edge or rising edge is aligned with the Local frame boundary,
this is controlled by the COPOL bit of the Control Register.
Zarlink Semiconductor Inc.
MT90870
15
Description
OL
= 10mA).
Data Sheet