mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 46

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

10.0
As operation of the memory BIST will corrupt existing data, this test must only be performed when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register when controlled via the microprocessor
interface.
11.0
The MT90870 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. JTAG is intended to be
used during the development cycle. The JTAG interface is operational when the MT90870 Core (V
powered at typical voltage levels.
11.1
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
•
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan Registers cells, under the control of the TAP
Controller in Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V
driven from an external source.
Test Access Port (TAP)
JTAG Port
Memory Built-In-Self-Test (BIST) Mode
stream
FP
Start Ch=254
Length=4
Start Ch=0
Length=256
Start Ch=0
Length=3
FP8i
Channels containing PRBS sequence
Once Started BER transmission continues until stopped by the BER control register:
frame boundary
0
0
0
Figure 17 - Examples of BER transmission channels
Note: Length = Start Chan. + No. of Consecutive channels
1
1
1
2
2
2
3
3
3
Zarlink Semiconductor Inc.
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Channels containing data (traffic)
254
254
254
255
255
255
0
0
0
1
1
1
2
2
2
DD_IO
Data Sheet
DD
when not
_core) is