mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 32

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

4.2
The input pin, BORS, selects whether the Backplane output streams, BSTo0-31 are set to high impedance at the
output of the MT90870 itself, or are always driven (active HIGH or active LOW) and a high impedance state, if
required on a per-channel basis, is invoked through an external interface circuit controlled by the BCSTo0-3
signals. Setting BORS to a LOW state will configure the output streams, BSTo0-31, to transmit bi-state channel
data with per-channel high-impedance determined by external circuits under the control of the BCSTo0-3 outputs.
Setting BORS to a HIGH state will configure the output streams, BSTo0-31, of the MT90870 to invoke a high-
impedance output on a per-channel basis.
The BORS pin is an asynchronous input and is expected to be hard-wired for a particular system application,
although it may be driven under logic control if preferred.
4.2.1
The data (channel control bit) transmitted by BCSTo0-3 replicates the Backplane Output Enable Bit (BE) of the
Backplane Connection Memory, with a LOW state indicating the channel to be set to High Impedance. See Section
12.4, Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE).
(16 Mb/s)
(8 Mb/s)
(4 Mb/s)
(2 Mb/s)
LCSTo0
LCSTo1
LSTo1
LSTo0
LSTo7
LSTo6
FP8o
C8o
Backplane High Impedance Control
BORS Set LOW, Non-32 Mb/s Mode
Figure 13 - Local Port External High Impedance Control Bit Timing (ST-Bus Mode)
Chan 127
Chan 31
Chan 63
1
Bit 0
Bit 0
Bit 0
0
Chan 0
7
Bit 7
Chan 0 Bit 7
Channel 0
6
Chan 0
5
Bit 6
Channel 0 Bit 7
4
Chan 0
3
Bit 5
Chan 0 Bit 6
2
Zarlink Semiconductor Inc.
Chan 0
1
Bit 4
MT90870
0
32
Chan 127
7
Bit 3
Chan 63 Bit 1
6
One C16o period
Channel 255 bits 7-0
Chan 127
5
Channel 31 Bit 0
Bit 2
4
Chan 127
3
Bit 1
Chan 63 Bit 0
2
Chan 127
1
Bit 0
0
7
Chan 0
Chan 0
Chan 0
Bit 7
Bit 7
Bit 7
Data Sheet
6