mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 62

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

The LOAR0 to LOAR15 registers are configured as follows:
13.8.1
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Local frame pulse.
13.9
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32 Mb/ s stream
operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072 MHz). The BOAR0 to
BOAR3 registers are configured as follows:
13.9.1
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the Backplane frame pulse.
mode, n = 0 to 15 for 32 Mb/s mode)
(where n = 0 to 15)
(where n = 0 to 31 for non-32 Mb/s
LOARn Bit
15-2
Backplane Output Advancement Registers (BOAR0 - 31)
1-0
Local Output Advancement Bits 1-0 (LOA1-LOA0)
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
BOARn Bit
15-2
1:0
Local Output Advancement
Table 28 - Local Output Advancement (LOAR) Programming Table
Table 29 - Backplane Output Advancement Register (BOAR) Bits
Clock Rate 131.072 MHz
Table 27 - Local Output Advancement Register (LOARn) Bits
Reserved
LOA(1:0)
Name
0 (Default)
-4 cycles
-6 cycles
-2 cycle
Reserved
BOA(1:0)
Name
Zarlink Semiconductor Inc.
Reset
MT90870
0
0
Reset
0
0
62
Corresponding Advancement Bits
Reserved
Local Output Advancement Register
Reserved
Backplane Output Advancement Register
LOA1
0
0
1
1
Description
Description
LOA0
0
1
0
1
Data Sheet