mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 43

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0, Microprocessor Port, and
Section 13.1, Control Register (CR) for details on microprocessor port access.
6.3
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power
up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register
(BPR) will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register
and Block Programming Register values, respectively.
6.3.1
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The Backplane Block Programming data bits, BBPD2-0, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded
with zeros as shown in Table 7.
The Block Programming Register bit, BPE will be automatically reset LOW within 125 us, to indicate completion of
memory programming. The Block Programming Mode can be terminated at any time prior to completion by setting
the BPE bit of the Block Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of LBPD2-0 and BBPD2-0 of the Block Programming Register, following a device
reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the
LORS and BORS pin conditions, see Pin Description for further details. The Local Connection Memory shall be
configured to select data from Channel 0 of Backplane input Stream 0 (BSTi0), and the Backplane Connection
Memory shall be configured to select data from Channel 0 of Local input Stream 0 (LSTi0). Alternative conditions
may be established by programming bits LBPD2-0 and BBPD2-0 of the Block Programming Register at the time of
setting Bit BPE to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane
Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
7.0
The MT90870 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (D0-15), 15-bit address bus (A0-14) and four control signals (CS, DS, R/W and DTA). The data
bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local
Connection and Data memories. Each Backplane memory has 8,192 locations and each Local memory has 4,096
BBPD2
LBPD2
Set the MBP bit in the Control Register from LOW to HIGH.
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6.
15
15
Connection Memory Block Programming
Microprocessor Port
Memory Block Programming Procedure
BBPD1
LBPD1
14
14
Table 7 - Backplane Connection Memory in Block Programming Mode
Table 6 - Local Connection Memory in Block Programming Mode
LBPD0
BBPD0
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