mt90870ag2 Zarlink Semiconductor, mt90870ag2 Datasheet - Page 29

• Manufacturer Part Number: mt90870ag2
• Description: Flexible 12 K Digital Switch F12kdx
• Manufacturer: Zarlink Semiconductor

As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 2:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0, LSTo0_Ch0, is transmitted on LCSTo0 and is
advanced, relative to the Frame Boundary, by 10 periods of C16o.
(2) The Channel Control Bit corresponding to Stream 14, Channel 0, LSTo14_Ch0, is transmitted on LCSTo0 in
advance of the Frame Boundary by three periods of output clock, C16o. Similarly, the Channel Control Bit for
LSTo15_Ch0, is advanced relative to the Frame Boundary by three periods of C16o, on LCSTo1.
The LCSTo0-1 outputs data at a constant data-rate of 16.384 Mb/s, independent of the data-rate selected for the
individual output streams, LSTo0-15. Streams at data-rates lower than 16.384 Mb/s will have the value of the
respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for 8.192 Mb/s
streams, four times for 4.096 Mb/s streams and eight times for 2.048 Mb/s streams. The channel control bit is not
repeated for 16.384 Mb/s streams.
Examples are presented, with reference to Table 2:
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus Mode) shows the channel control bits for
LCSTo0 and LCSTo1 in one possible scenario which includes stream LSTo0 at a data-rate of 16.384 Mb/s, LSTo1
at 8.192 Mb/s, LSTo6 at 4.096 Mb/s and LSTo7 at 2.048 Mb/s. All remaining streams are operated at a data-rate of
16.384 Mb/s.
4.1.2
The Local Output Enable Bit (LE) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams, LSTo0-15. Programming the LE bit to a LOW state will set the
stream output of the MT90870 to High Impedance for the duration of the channel period. See Section 12.3, Local
Connection Memory Bit Definition, for programming details.
The LCSTo0-1 outputs remain active.
2039
2040
2041
2042
2043
2044
2045
2046
Period
(3) With stream LSTo4 selected to operate at a data-rate of 2.048 Mb/s, the value of the Channel Control
Bit for Channel 0 will be transmitted during the C16o clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and
48.
(4) With stream LSTo8 operated at a data-rate of 8.192 Mb/s, the value of the Channel Control Bit for
Channel 1 will be transmitted during the C16o clock period nos. 9 and 17.
C16o
1
LORS Set HIGH
0
2
4
6
8
10
12
14
3-3
3-1
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
3-2
Allocated Stream No.
LCSTo0
1
3
5
7
9
11
13
15
LCSTo1
3-2
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
16 Mb/s
Zarlink Semiconductor Inc.
MT90870
29
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Allocated Channel No.
8 Mb/s
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
4 Mb/s
2
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
2 Mb/s
Data Sheet