at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 447

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

31.6
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write
operations to the UDP registers including the UDP_TXVC register.
Table 31-4.
Notes:
8549A–CAP–10/08
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
.
.
.
See Note:
0x050
.
.
.
See Note:
0x070
0x074
0x078 - 0xFC
USB Device Port (UDP) User Interface
1. The addresses of the UDP_ CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1).
2. The addresses of the UDP_ FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1).
3. See Warning above the
(1)
(2)
UDP Memory Map
Register
Frame Number Register
Global State Register
Function Address Register
Reserved
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Interrupt Status Register
Interrupt Clear Register
Reserved
Reset Endpoint Register
Reserved
Endpoint 0 Control and Status Register
.
.
.
Endpoint
Endpoint 0 FIFO Data Register
.
.
.
Endpoint
Reserved
Transceiver Control Register
Reserved
5
5
Control and Status Register
FIFO Data Register
”UDP Memory Map”
on this page.
Name
UDP_ FRM_NUM
UDP_ GLB_STAT
UDP_ FADDR
–
UDP_ IER
UDP_ IDR
UDP_ IMR
UDP_ ISR
UDP_ ICR
–
UDP_ RST_EP
–
UDP_CSR0
UDP_CSR5
UDP_ FDR0
UDP_
–
UDP_ TXVC
–
FDR5
(3)
Access
Read
Read/Write
Read/Write
–
Write
Write
Read
Read
Write
–
Read/Write
–
Read/Write
Read/Write
Read/Write
Read/Write
–
Read/Write
–
AT91CAP7E
0x0000_0000
0x0000_0100
0x0000_1200
Reset State
0x0000_0000
–
0x0000_XX00
–
–
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
–
0x0000_0100
–
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