at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 152

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

21.10.2
Figure 21-22. TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
21.10.3
152
D[31:0]
A [25:2]
NCS0
NWE
MCK
NRD
AT91CAP7E
TDF Optimization Enabled (TDF_MODE = 1)
TDF Optimization Disabled (TDF_MODE = 0)
read access on NCS0 (NRD controlled)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the
SMC takes advantage of the setup period of the next access to optimize the number of wait
states cycle to insert.
Figure 21-22
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that
the data float period is ended when the second access begins. If the hold period of the read1
controlling signal overlaps the data float period, no additional tdf wait states will be inserted.
Figure
with no TDF optimization.
• read access followed by a read access on another chip select,
• read access followed by a write access on another chip select,
• read access followed by a write access on the same chip select,
21-23,
shows a read access controlled by NRD, followed by a write access controlled by
Figure 21-24
NRD_HOLD= 4
TDF_CYCLES = 6
and
Figure 21-25
Read to Write
Wait State
NWE_SETUP= 3
illustrate the cases:
write access on NCS0 (NWE controlled)
8549A–CAP–10/08