at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 234

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

24.2.10.10
Register Name:
Access Type:
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
• DIVB: Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLLB Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULB: PLL B Multiplier
0 = The PLL B is deactivated.
1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock
234
DIVB
0
1
2 - 255
31
23
15
–
7
0
0
1
1
AT91CAP7E
OUTB
PMC Clock Generator PLL B Register
USBDIV
30
22
14
–
6
CKGR_PLLBR
Read/Write
0
1
0
1
29
21
13
5
USBDIV
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVB.
Divider for USB Clock(s)
Divider output is PLL B clock output.
Divider output is PLL B clock output divided by 2.
Divider output is PLL B clock output divided by 4.
Reserved.
28
20
12
4
MULB
DIVB
27
19
11
–
3
PLLBCOUNT
26
18
10
2
MULB
25
17
9
1
8549A–CAP–10/08
24
16
8
0