at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 430

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

31.2
Figure 31-1. Block Diagram
430
MCK
UDPCK
udp_int
external_resume
Block Diagram
AT91CAP7E
Atmel Bridge
MCU
APB
Bus
to
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a
48 MHz clock used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must be
also negotiated with the host during the enumeration.
U
e
n
e
a
e
s
c
r
I
t
r
f
W
a
p
p
e
Master Clock
Domain
r
r
USB Device
RAM
FIFO
Dual
Port
Recovered 12 MHz
Domain
W
a
p
p
e
r
r
Suspend/Resume Logic
12 MHz
Interface
Engine
Serial
SIE
txoen
eopn
txd
rxdm
rxd
rxdp
Transceiver
Embedded
USB
8549A–CAP–10/08
DM
DP