at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 173

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

22. SDRAM Controller (HSDRAMC)
22.1
22.2
22.3
22.4
8549A–CAP–10/08
Description
I/O Lines Description
Application Example
Software Interface
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing
the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges
from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit),
half-word (16-bit) and word (32-bit) accesses.
The SDRAM Controller supports a read or write burst length of one location. It keeps
track of the active row in each bank, thus maximizing SDRAM performance, e.g., the
application may be placed in one bank and data in the other banks. So as to optimize per-
formance, it is advisable to avoid accessing different rows in the same bank.
The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access
depending on the frequency.
The different modes available - self-refresh, power-down and deep power-down modes - mini-
mize power consumption on the SDRAM device.
Table 22-1.
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
Name
SDCK
SDCKE
SDCS
BA[1:0]
RAS
CAS
SDWE
NBS[3:0]
SDRAMC_A[12:0]
D[31:0]
Table 22-2
I/O Line Description
to
Description
SDRAM Clock
SDRAM Clock Enable
SDRAM Controller Chip Select
Row Signal
Column Signal
SDRAM Write Enable
Data Mask Enable Signals
Address Bus
Data Bus
Bank Select Signals
Table 22-7
illustrate the SDRAM device memory mapping seen by the
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
I/O
AT91CAP7E
Active Level
High
Low
Low
Low
Low
Low
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