at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 252

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

Figure 25-10. Fast Forcing
25.5.6
252
AT91CAP7E
Protect Mode
Source 0 _ FIQ
The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0
(AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not
clear the Source 0 when the fast forcing feature is used and the interrupt source should be
cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
All enabled and pending interrupt sources that have the fast forcing feature enabled and that are
programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command
Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues operating normally and becomes one of
the Fast Interrupt sources.
The Protect Mode permits reading the Interrupt Vector Register without performing the associ-
ated automatic operations. This is necessary when working with a debug system. When a
debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applica-
tions and updates the opened windows, it might read the AIC User Interface and thus the IVR.
This has undesirable consequences:
In either case, an End of Interrupt command is necessary to acknowledge and to restore the
context of the AIC. This operation is generally not performed by the debug system as the debug
system would become strongly intrusive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing PROT in AIC_DCR (Debug Control Register)
at 0x1 enables the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access
is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary
data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the
Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is
written.
Source n
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
Automatic Clear
Automatic Clear
Input Stage
Input Stage
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.
AIC_IPR
AIC_IPR
AIC_IMR
AIC_IMR
AIC_FFSR
Manager
Priority
8549A–CAP–10/08
nIRQ
nFIQ