at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 17

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

7.3.1
7.3.2
7.4
8549A–CAP–10/08
Peripheral DMA Controller
Matrix Masters
Matrix Slaves
The Bus Matrix of the AT91CAP7E manages four Masters, which means that each master can
perform an access concurrently with others, as long as the slave it accesses is available.
Each Master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decoding. There are two independent
masters available for an external FPGA.
Table 7-1.
The Bus Matrix of the AT91CAP7E manages nine Slaves. Each Slave has its own arbiter, thus
allowing to program a different arbitration per Slave.
There are four independent slaves available for the FPGA Interface.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
Slave 9
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• 9 channels
of the processor.
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Peripheral Interface
– One for the Analog to Digital Converter (ADC)
– Two for peripherals implemented through the FPGA Interface
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM 96 Kbytes
Internal SRAM 64 Kbytes
Internal ROM 256 Kbytes
FPGA Slave A
FPGA Slave B
FPGA Slave C
FPGA Slave D
Unavailable
External Bus Interface
Peripheral Bridge
ARM7TDMI
Peripheral DMA Controller
FPGA Master A
FPGA Master B
AT91CAP7E
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