at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 233

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

24.2.10.9
Register Name:
Access Type:
Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
• PLLACOUNT: PLL A Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLL A Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULA: PLL A Multiplier
0 = The PLL A is deactivated.
1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1.
8549A–CAP–10/08
DIVA
0
1
2 - 255
31
23
15
–
7
OUTA
PMC Clock Generator PLL A Register
30
22
14
–
6
CKGR_PLLAR
Read/Write
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the Main Clock divided by DIVA.
28
20
12
–
4
MULA
DIVA
27
19
11
–
3
PLLACOUNT
26
18
10
2
MULA
25
17
9
1
AT91CAP7E
24
16
8
0
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