at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 211

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

24.1.5.2
8549A–CAP–10/08
Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On
reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that
depends on the respective source signal frequency and on the parameters DIV and MUL. The
factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the
corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be
performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or
LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLA-
COUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the
PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0.
At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The
user has to load the number of Slow Clock cycles required to cover the PLL transient time into
the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL
and its target frequency can be calculated using a specific tool provided by Atmel.
For PLLB, the values of DIV and MUL should be set to produce an input clock frequency of
12MHz and an output clock frequency of 96MHz for optimal operation for USB support. Any
other settings will likely result in result in reduced quality of the PLLB output clock.
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