at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 138

• Manufacturer Part Number: at91cap7e
• Description: Customizable Microcontroller
• Manufacturer: ATMEL Corporation

21.8.1
Figure 21-8. Standard Read Cycle
21.8.1.1
138
AT91CAP7E
Read Waveforms
NRD Waveform
NBS0,NBS1,
NBS2,NBS3,
A0, A1
D[31:0]
A[25:2]
MCK
NRD
NCS
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
NCS_RD_SETUP
falling edge;
rising edge;
rising edge.
{A[25:2], A1, A0} for 8-bit devices
{A[25:2], A1} for 16-bit devices
A[25:2] for 32-bit devices.
NRD_SETUP
Figure
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
21-8.
NRD_HOLD
NCS_RD_HOLD
8549A–CAP–10/08