pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 59

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pxf4336

Manufacturer Part Number
pxf4336
Description
Abm Premium Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
3.2.8
The ABM-P provides three different reset sources, as shown in
hardware signal RESET affects the entire device. The self-clearing software reset bit
‘SWRES’ in register
reset bit ‘ERCSWRES’ in register
This bit is not self-clearing and allows the entire ERC unit to be kept in reset state while
the rest of the device is working.
Hardware reset as well as software reset bit ‘SWRES’ completely initialize the device
into power-on reset state.
Figure 3-9
Note: Initialization of external and internal RAM must be started by software via
Data Sheet
command bits ‘INITRAM’ and ‘INITSDRAM’ in register
following the device reset.
Reset System
Reset System Overview
Test/
Clocks
BSCAN/
SPI
“MODE1” on Page 373
AAL5
ERC
SSRAM
uP IF
IF
ARC
QCI
“MODE1” on Page 373
IF
SWRES
bit 15
Cell Handler downstream
59
Cell Handler upstream
SDRAM Interface (dn)
SDRAM Interface (up)
bit 14
SWRES
also affects the entire device. The software
ERC
Manager
Buffer
(BM)
affects only the ERC unit.
Register ‘MODE 1’
Scheduler
Functional Description
“MODE1” on Page 373
Queue
(QS)
ARC
PXF 4336 V1.1
Figure
2001-12-17
3-9. The
ABM-P

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