pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 341

• Manufacturer Part Number: pxf4336
• Description: Abm Premium Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

7.2.25
Register 103 PLL1CONF
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
DPLL1 generates a clock that is an alternative clock source for the ABM-P. The DPLL1
is fed by clock input signal ‘SYSCLK’. Signal ‘SYSCLKSEL’ determines the clock source
of the ABM-P.
Locked1
Div2En1
Div1En1
Data Sheet
Locked1 Div2En1 Div1En1 BYPAS
15
7
PLL Control Registers
M1(1:0)
PLL1 Configuration Register
Section 3.2.7 “Clocking System” on Page 55
14
DPLL1 Locked
(read only)
1
0
Division Factor 2 Enable for DPLL1
This bit enables one of the additional divide by 2 factors subsequent
to the DPLL1 output.
0
1
Division Factor 1 Enable for DPLL1
This bit enables one of the additional divide by 2 factors subsequent
to the DPLL1 output.
6
Read/Write
0000
PLL1CONF
Written and Read by CPU
H
13
5
DPLL1 is locked based on the current parameter
setting.
DPLL1 is in transient status.
Division Factor 2 disabled.
Division Factor 2 enabled.
D7
H
12
S1
4
341
PU1
11
3
N1(5:0)
RES1
10
2
provides the details.
Register Description
PXF 4336 V1.1
9
1
M1(3:2)
2001-12-17
ABM-P
8
0