pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 368
pxf4336
Manufacturer Part Number
pxf4336
Description
Abm Premium Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4336.pdf
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7.2.30
Register 123 MAR
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
Start_W
Start_R
MAR(4:0)
Data Sheet
Unused Start_W
15
7
RAM Select Registers
Memory Address Register
14
This command bit starts the Write procedure to the internal RAM/
table addressed by bit field MAR(4:0). The specific data transfer
and mask registers must be prepared appropriately in advance.
This bit is automatically cleared after completion of the Write
procedure.
Simplifies Read access without need to touch the mask registers
Memory Address
This bit field selects one of the internal RAM/tables for Read or
Write operation:
00000
00001
00010
00011
00101
00111
01000
6
Read/Write
0000
MAR
Written by CPU to address internal RAM/tables for Read
or Write operation via transfer registers
H
Start_R
13
5
LCI: LCI Table RAM (see page 237)
TCT: Traffic Class Table (see page 241)
QCT: Queue Configuration Table (see page 258)
SBOC: Scheduler Block Occupation Table (see page
270)
DTC: DBA Threshold Crossing Table (see page 235)
MGT: Merge Group Table (see page 277)
QCI: Queue Congestion Indication Table (see page
286)
EB
H
12
Unused(9:2)
4
368
11
3
MAR(4:0)
10
2
Register Description
PXF 4336 V1.1
9
1
2001-12-17
ABM-P
8
0
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