pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 236

• Manufacturer Part Number: pxf4336
• Description: Abm Premium Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Register 35 DTCT
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
DTCSBE(15:0)
Data Sheet
15
7
DTC Transfer Register
14
DBA Threshold Crossing Scheduler Block Event
Each bit indicates that a DBA Threshold Crossing Event has
occurred in a specific Scheduler Block (SB). The Threshold
Crossing type must then be read from the respective SBOC table
entry (see Register 50: SBOC0 ).
The Scheduler Block j is determined from the bit-position N in bit
field DTCSBE(15:8) and the Entry number (Register WAR bit field
’EntrySel(3:0)’ and bit ’Core’):
Core=’0’
Core=’1’
Note: The DTCSBE(15:0) entries are automatically cleared on
6
Read
0000
DTCT
Read by CPU
read. Any new event (bit set by ABM-P) generates an
interrupt in register ISRDBA ( see Register 121: ISRDBA).
H
13
5
Upstream Events:
j
Downstream Events:
j
SBUp
SBDn
:= EntrySel(3:0) * 16 + N
:= EntrySel(3:0) * 16 + N
3A
H
DTCSBE(15:8)
DTCSBE(7:0)
12
4
236
11
3
10
2
Register Description
PXF 4336 V1.1
9
1
2001-12-17
ABM-P
8
0