pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 58

• Manufacturer Part Number: pxf4336
• Description: Abm Premium Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

In this example, signal SYSCLKSEL must be connected to V
core clock to the DPLL1 output. Signal ERCCLKSEL must be connected to V
connect the alternative ERC clock to the DPLL2 output. Signal ERCFREQSEL must be
connected to V
(which is DPLL2 output in this example). (Please refer to
DPLL1 Programming
A reasonable value for parameter M1 in register
which results in
f
Now a possible value for parameter N1 is N1 = 25 which results in
f
To achieve the 52 MHz core clock division factor 1 shall be enabled.
Thus, for this example the value 3B19
The conditions given above are met because f
(n=25) and f
Note: Multiple combinations of parameters are possible to achieve a 52 MHz clock in
DPLL2 Programming
A reasonable value for parameter M2 in register
which results in
f
Now a possible value for parameter N2 is N2 = 29 which results in
f
The division factor shall be enabled to maintain the 60 MHz clock frequency.
Thus for this example the value 3B1D
The conditions given above are met because f
(n=29) and f
Note: Multiple combinations of parameters are possible to achieve a 60 MHz clock in
3.2.7.4
After power-on reset, both DPLLs are in bypass mode which means that signal
‘SYSCLK’ is directly feeding the internal core clock and internal ERC core clock. After
basic configuration of at least the DPLL configuration registers, the bypass can be
disabled which will make a glitch-free adjustment of the internal clocks to the selected
frequency.
Data Sheet
1
2
1
2
= 52 MHz / (12 + 1) = 4 MHz.
= 4 MHz * (25 + 1) = 104 MHz.
= 52 MHz / (12 + 1) = 4 MHz.
= 4 MHz * (29 + 1) = 120 MHz.
this example.
this example.
Initialization Phase
2
2
=104 MHz is between 100 and 200 MHz.
=120 MHz is between 100 and 200 MHz.
DD
to connect the internal ERC core clock to the alternative ERC clock
H
H
must be programmed to register PLL2CONF.
must be programmed to register PLL1CONF.
58
“PLL1CONF” on Page 341
“PLL2CONF” on Page 343
1
1
=4 MHz is in the range of 2..6 MHz
=4 MHz is in the range of 2..6 MHz
Figure
SS
Functional Description
to connect the internal
3-7)
PXF 4336 V1.1
is M1 = 12
is M2 = 12
2001-12-17
ABM-P
SS
to