mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 373

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

21.8 Low-Power Modes
21.8.1 Wait Mode
21.8.2 Stop Mode
MC68HC908AS60 — Rev. 1.0
NOTE:
NOTE:
halted is after at least one byte plus two extra logic 1s have been
transmitted. The receiver will pick this up as an error and relay it in the
state vector register as an invalid symbol error.
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
This subsection describes wait mode and stop mode.
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in
BDLC control register 1 (BCR1) is previously clear. In BDLC wait mode,
the BDLC cannot drive any data.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BDLC control register 1 (BCR1) is previously set (see
21.7.2 BDLC Control Register 1
results in less of a power saving, but the BDLC is guaranteed to receive
correctly the message which woke it up, since the BDLC internal
operating clocks are kept running.
Ensuring that all transmissions are complete or aborted before putting
the BDLC into wait mode is important.
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BDLC control register 1
(BCR1) is previously set. This is the lowest power mode that the BDLC
can enter.
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Byte Data Link Controller-Digital (BDLC-D)
Low-Power Modes
Technical Data