mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 254

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mc68hc908as60

Manufacturer Part Number
mc68hc908as60
Description
Mc68hc908as60 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Serial Communications Interface (SCI)
17.9.6 SCI Data Register
Technical Data
NOTE:
Address:
RPF — Reception-in-Progress Flag Bit
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
R7/T7:R0/T0 — Receive/Transmit Data Bits
Do not use read-modify-write instructions on the SCI data register.
Reset:
Read:
Write:
reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the RxD pin followed by another break character. Reset clears the
BKF bit.
This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.
Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Break character detected
0 = No break character detected
1 = Reception in progress
0 = No reception in progress
Serial Communications Interface (SCI)
$0018
Bit 7
R7
T7
Go to: www.freescale.com
Figure 17-15. SCI Data Register (SCDR)
R6
T6
6
R5
T5
5
Unaffected by reset
R4
T4
4
R3
T3
3
MC68HC908AS60 — Rev. 1.0
R2
T2
2
R1
T1
1
Bit 0
R0
T0

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